Impres: integrated monitoring for processor reliability and security
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| Titel: | Impres: integrated monitoring for processor reliability and security |
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| Autoren: | Roshan G. Ragel, Sri Parameswaran |
| Weitere Verfasser: | The Pennsylvania State University CiteSeerX Archives |
| Quelle: | http://www.cse.unsw.edu.au/~sridevan/index_files/31.4s-ragel.pdf. |
| Verlagsinformationen: | ACM Press |
| Publikationsjahr: | 2006 |
| Bestand: | CiteSeerX |
| Schlagwörter: | Categories and Subject Descriptors, B.8.1 [Performance and Reliability, Reliability, Testing, and Fault-Tolerance General Terms, Design, Performance, Security Keywords, Detecting Code Injection Attacks, Basic Block Checksumming, Checksum Encryption, Bit Flips Detection |
| Beschreibung: | Security and reliability in processor based systems are concerns requiring adroit solutions. Security is often compromised by code injection attacks, jeopardizing even ‘trusted software’. Reliability is of concern where unintended code is executed in modern processors with ever smaller feature sizes and low voltage swings causing bit flips. Countermeasures by software-only approaches increase code size by large amounts and therefore significantly reduce performance. Hardware assisted approaches add extensive amounts of hardware monitors and thus incur unacceptably high hardware cost. This paper presents a novel hardware/software technique at the granularity of micro-instructions to reduce overheads considerably. Experiments show that our technique incurs an additional hardware overhead of 0.91 % and clock period increase of 0.06%. Average clock cycle and code size overheads are just 11.9 % and 10.6 % for five industry standard application benchmarks. These overheads are far smaller than have been previously encountered. |
| Publikationsart: | text |
| Dateibeschreibung: | application/pdf |
| Sprache: | English |
| Relation: | http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.133.339 |
| Verfügbarkeit: | http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.133.339 http://www.cse.unsw.edu.au/~sridevan/index_files/31.4s-ragel.pdf |
| Rights: | Metadata may be used without restrictions as long as the oai identifier remains attached to it. |
| Dokumentencode: | edsbas.766D8C4B |
| Datenbank: | BASE |
Nájsť tento článok vo Web of Science | Abstract: | Security and reliability in processor based systems are concerns requiring adroit solutions. Security is often compromised by code injection attacks, jeopardizing even ‘trusted software’. Reliability is of concern where unintended code is executed in modern processors with ever smaller feature sizes and low voltage swings causing bit flips. Countermeasures by software-only approaches increase code size by large amounts and therefore significantly reduce performance. Hardware assisted approaches add extensive amounts of hardware monitors and thus incur unacceptably high hardware cost. This paper presents a novel hardware/software technique at the granularity of micro-instructions to reduce overheads considerably. Experiments show that our technique incurs an additional hardware overhead of 0.91 % and clock period increase of 0.06%. Average clock cycle and code size overheads are just 11.9 % and 10.6 % for five industry standard application benchmarks. These overheads are far smaller than have been previously encountered. |
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