FPGA Implementation of a Recently Published Signature Scheme
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| Title: | FPGA Implementation of a Recently Published Signature Scheme |
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| Authors: | Beuchat, Jean-Luc, Sendrier, Nicolas, Tisserand, Arnaud, Villard, Gilles |
| Contributors: | Computer arithmetic (ARENAIRE), Centre Inria de l'Université Grenoble Alpes, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-Laboratoire de l'Informatique du Parallélisme (LIP), École normale supérieure de Lyon (ENS de Lyon), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)-École normale supérieure de Lyon (ENS de Lyon), Université de Lyon-Centre National de la Recherche Scientifique (CNRS), INRIA, LIP |
| Source: | https://inria.hal.science/inria-00077045 ; [Research Report] RR-5158, LIP RR-2004-14, INRIA, LIP. 2004. |
| Publisher Information: | CCSD |
| Publication Year: | 2004 |
| Collection: | HAL Lyon 1 (University Claude Bernard Lyon 1) |
| Subject Terms: | FPGA IMPLEMENTATION, CODE-BASED CRYPTOSYSTEMS, DIGITAL SIGNATURE, CRYPTOGRAPHY, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH] |
| Description: | An algorithm producing cryptographic digital signatures less than 100 bits long with a security level matching nowadays standards has been recently proposed by Courtois, Finiasz, and Sendrier. This scheme is based on error correcting codes and consists in generating a large number of instances of a decoding problem until one of them is solved (about 9!=362880 attempts are needed). A careful software implementation requires more than one minute on a 2GHz Pentium 4 for signing. We propose a first hardware architecture which allows to sign a document in 0.86 second on an XCV300E-7 FPGA, hence making the algorithm practical. |
| Document Type: | report |
| Language: | English |
| Availability: | https://inria.hal.science/inria-00077045 https://inria.hal.science/inria-00077045v1/document https://inria.hal.science/inria-00077045v1/file/RR-5158.pdf |
| Rights: | info:eu-repo/semantics/OpenAccess |
| Accession Number: | edsbas.67985BF2 |
| Database: | BASE |
Nájsť tento článok vo Web of Science | Abstract: | An algorithm producing cryptographic digital signatures less than 100 bits long with a security level matching nowadays standards has been recently proposed by Courtois, Finiasz, and Sendrier. This scheme is based on error correcting codes and consists in generating a large number of instances of a decoding problem until one of them is solved (about 9!=362880 attempts are needed). A careful software implementation requires more than one minute on a 2GHz Pentium 4 for signing. We propose a first hardware architecture which allows to sign a document in 0.86 second on an XCV300E-7 FPGA, hence making the algorithm practical. |
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