FPGA Implementation of a Recently Published Signature Scheme

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Titel: FPGA Implementation of a Recently Published Signature Scheme
Autoren: Laboratoire de l'informatique du parallélisme, Beuchat, Jean-Luc, Sendrier, Nicolas, Tisserand, Arnaud, Villard, Gilles
Quelle: http://www.ens-lyon.fr/LIP/Pub/Rapports/RR/RR2004/RR2004-14.ps.gz.
Publikationsjahr: 2004
Bestand: LARA - Libre accès aux rapports scientifiques et techniques (INIST - Institut de l'Information Scientifique et Technique / CNRS)
Schlagwörter: Cryptography, Digital signature, Code-based cryptosystems, FPGA implementation
Beschreibung: (eng) An algorithm producing cryptographic digital signatures less than 100 bits long with a security level matching nowadays standards has been recently proposed by Courtois, Finiasz, and Sendrier. This scheme is based on error correcting codes and consists in generating a large number of instances of a decoding problem until one of them is solved (about 9!=362880 attempts are needed). A careful software implementation requires more than one minute on a 2GHz Pentium 4 for signing. We propose a first hardware architecture which allows to sign a document in 0.86 second on an XCV300E-7 FPGA, hence making the algorithm practical.
Publikationsart: report
Dateibeschreibung: 2+8p; 314955 bytes; 23 bytes; application/pdf; application/octet-stream
Sprache: English
Relation: LIP-RR - 2004-14; http://hdl.handle.net/2332/1006
Verfügbarkeit: http://hdl.handle.net/2332/1006
Rights: http://lara.inist.fr/utilisation.jsp
Dokumentencode: edsbas.64AF7DCF
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  Data: FPGA Implementation of a Recently Published Signature Scheme
– Name: Author
  Label: Authors
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  Data: <searchLink fieldCode="AR" term="%22Laboratoire+de+l'informatique+du+parallélisme%22">Laboratoire de l'informatique du parallélisme</searchLink><br /><searchLink fieldCode="AR" term="%22Beuchat%2C+Jean-Luc%22">Beuchat, Jean-Luc</searchLink><br /><searchLink fieldCode="AR" term="%22Sendrier%2C+Nicolas%22">Sendrier, Nicolas</searchLink><br /><searchLink fieldCode="AR" term="%22Tisserand%2C+Arnaud%22">Tisserand, Arnaud</searchLink><br /><searchLink fieldCode="AR" term="%22Villard%2C+Gilles%22">Villard, Gilles</searchLink>
– Name: TitleSource
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  Data: <i>http://www.ens-lyon.fr/LIP/Pub/Rapports/RR/RR2004/RR2004-14.ps.gz</i>.
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  Label: Publication Year
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  Data: 2004
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  Data: LARA - Libre accès aux rapports scientifiques et techniques (INIST - Institut de l'Information Scientifique et Technique / CNRS)
– Name: Subject
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  Data: <searchLink fieldCode="DE" term="%22Cryptography%22">Cryptography</searchLink><br /><searchLink fieldCode="DE" term="%22Digital+signature%22">Digital signature</searchLink><br /><searchLink fieldCode="DE" term="%22Code-based+cryptosystems%22">Code-based cryptosystems</searchLink><br /><searchLink fieldCode="DE" term="%22FPGA+implementation%22">FPGA implementation</searchLink>
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  Label: Description
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  Data: (eng) An algorithm producing cryptographic digital signatures less than 100 bits long with a security level matching nowadays standards has been recently proposed by Courtois, Finiasz, and Sendrier. This scheme is based on error correcting codes and consists in generating a large number of instances of a decoding problem until one of them is solved (about 9!=362880 attempts are needed). A careful software implementation requires more than one minute on a 2GHz Pentium 4 for signing. We propose a first hardware architecture which allows to sign a document in 0.86 second on an XCV300E-7 FPGA, hence making the algorithm practical.
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      – Text: English
    Subjects:
      – SubjectFull: Cryptography
        Type: general
      – SubjectFull: Digital signature
        Type: general
      – SubjectFull: Code-based cryptosystems
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      – SubjectFull: FPGA implementation
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      – TitleFull: FPGA Implementation of a Recently Published Signature Scheme
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