FPGA Implementation of a Recently Published Signature Scheme
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| Titel: | FPGA Implementation of a Recently Published Signature Scheme |
|---|---|
| Autoren: | Laboratoire de l'informatique du parallélisme, Beuchat, Jean-Luc, Sendrier, Nicolas, Tisserand, Arnaud, Villard, Gilles |
| Quelle: | http://www.ens-lyon.fr/LIP/Pub/Rapports/RR/RR2004/RR2004-14.ps.gz. |
| Publikationsjahr: | 2004 |
| Bestand: | LARA - Libre accès aux rapports scientifiques et techniques (INIST - Institut de l'Information Scientifique et Technique / CNRS) |
| Schlagwörter: | Cryptography, Digital signature, Code-based cryptosystems, FPGA implementation |
| Beschreibung: | (eng) An algorithm producing cryptographic digital signatures less than 100 bits long with a security level matching nowadays standards has been recently proposed by Courtois, Finiasz, and Sendrier. This scheme is based on error correcting codes and consists in generating a large number of instances of a decoding problem until one of them is solved (about 9!=362880 attempts are needed). A careful software implementation requires more than one minute on a 2GHz Pentium 4 for signing. We propose a first hardware architecture which allows to sign a document in 0.86 second on an XCV300E-7 FPGA, hence making the algorithm practical. |
| Publikationsart: | report |
| Dateibeschreibung: | 2+8p; 314955 bytes; 23 bytes; application/pdf; application/octet-stream |
| Sprache: | English |
| Relation: | LIP-RR - 2004-14; http://hdl.handle.net/2332/1006 |
| Verfügbarkeit: | http://hdl.handle.net/2332/1006 |
| Rights: | http://lara.inist.fr/utilisation.jsp |
| Dokumentencode: | edsbas.64AF7DCF |
| Datenbank: | BASE |
| FullText | Text: Availability: 0 CustomLinks: – Url: http://hdl.handle.net/2332/1006# Name: EDS - BASE (s4221598) Category: fullText Text: View record from BASE – Url: https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=EBSCO&SrcAuth=EBSCO&DestApp=WOS&ServiceName=TransferToWoS&DestLinkType=GeneralSearchSummary&Func=Links&author=parall%C3%A9lisme%20Ldld Name: ISI Category: fullText Text: Nájsť tento článok vo Web of Science Icon: https://imagesrvr.epnet.com/ls/20docs.gif MouseOverText: Nájsť tento článok vo Web of Science |
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| Items | – Name: Title Label: Title Group: Ti Data: FPGA Implementation of a Recently Published Signature Scheme – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Laboratoire+de+l'informatique+du+parallélisme%22">Laboratoire de l'informatique du parallélisme</searchLink><br /><searchLink fieldCode="AR" term="%22Beuchat%2C+Jean-Luc%22">Beuchat, Jean-Luc</searchLink><br /><searchLink fieldCode="AR" term="%22Sendrier%2C+Nicolas%22">Sendrier, Nicolas</searchLink><br /><searchLink fieldCode="AR" term="%22Tisserand%2C+Arnaud%22">Tisserand, Arnaud</searchLink><br /><searchLink fieldCode="AR" term="%22Villard%2C+Gilles%22">Villard, Gilles</searchLink> – Name: TitleSource Label: Source Group: Src Data: <i>http://www.ens-lyon.fr/LIP/Pub/Rapports/RR/RR2004/RR2004-14.ps.gz</i>. – Name: DatePubCY Label: Publication Year Group: Date Data: 2004 – Name: Subset Label: Collection Group: HoldingsInfo Data: LARA - Libre accès aux rapports scientifiques et techniques (INIST - Institut de l'Information Scientifique et Technique / CNRS) – Name: Subject Label: Subject Terms Group: Su Data: <searchLink fieldCode="DE" term="%22Cryptography%22">Cryptography</searchLink><br /><searchLink fieldCode="DE" term="%22Digital+signature%22">Digital signature</searchLink><br /><searchLink fieldCode="DE" term="%22Code-based+cryptosystems%22">Code-based cryptosystems</searchLink><br /><searchLink fieldCode="DE" term="%22FPGA+implementation%22">FPGA implementation</searchLink> – Name: Abstract Label: Description Group: Ab Data: (eng) An algorithm producing cryptographic digital signatures less than 100 bits long with a security level matching nowadays standards has been recently proposed by Courtois, Finiasz, and Sendrier. This scheme is based on error correcting codes and consists in generating a large number of instances of a decoding problem until one of them is solved (about 9!=362880 attempts are needed). A careful software implementation requires more than one minute on a 2GHz Pentium 4 for signing. We propose a first hardware architecture which allows to sign a document in 0.86 second on an XCV300E-7 FPGA, hence making the algorithm practical. – Name: TypeDocument Label: Document Type Group: TypDoc Data: report – Name: Format Label: File Description Group: SrcInfo Data: 2+8p; 314955 bytes; 23 bytes; application/pdf; application/octet-stream – Name: Language Label: Language Group: Lang Data: English – Name: NoteTitleSource Label: Relation Group: SrcInfo Data: LIP-RR - 2004-14; http://hdl.handle.net/2332/1006 – Name: URL Label: Availability Group: URL Data: http://hdl.handle.net/2332/1006 – Name: Copyright Label: Rights Group: Cpyrght Data: http://lara.inist.fr/utilisation.jsp – Name: AN Label: Accession Number Group: ID Data: edsbas.64AF7DCF |
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| RecordInfo | BibRecord: BibEntity: Languages: – Text: English Subjects: – SubjectFull: Cryptography Type: general – SubjectFull: Digital signature Type: general – SubjectFull: Code-based cryptosystems Type: general – SubjectFull: FPGA implementation Type: general Titles: – TitleFull: FPGA Implementation of a Recently Published Signature Scheme Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Laboratoire de l'informatique du parallélisme – PersonEntity: Name: NameFull: Beuchat, Jean-Luc – PersonEntity: Name: NameFull: Sendrier, Nicolas – PersonEntity: Name: NameFull: Tisserand, Arnaud – PersonEntity: Name: NameFull: Villard, Gilles IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 01 Type: published Y: 2004 Identifiers: – Type: issn-locals Value: edsbas Titles: – TitleFull: http://www.ens-lyon.fr/LIP/Pub/Rapports/RR/RR2004/RR2004-14.ps.gz Type: main |
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