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FPGA Implementation of a Recently Published Signature Scheme

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Bibliographic Details
Title: FPGA Implementation of a Recently Published Signature Scheme
Authors: Laboratoire de l'informatique du parallélisme, Beuchat, Jean-Luc, Sendrier, Nicolas, Tisserand, Arnaud, Villard, Gilles
Source: http://www.ens-lyon.fr/LIP/Pub/Rapports/RR/RR2004/RR2004-14.ps.gz.
Publication Year: 2004
Collection: LARA - Libre accès aux rapports scientifiques et techniques (INIST - Institut de l'Information Scientifique et Technique / CNRS)
Subject Terms: Cryptography, Digital signature, Code-based cryptosystems, FPGA implementation
Description: (eng) An algorithm producing cryptographic digital signatures less than 100 bits long with a security level matching nowadays standards has been recently proposed by Courtois, Finiasz, and Sendrier. This scheme is based on error correcting codes and consists in generating a large number of instances of a decoding problem until one of them is solved (about 9!=362880 attempts are needed). A careful software implementation requires more than one minute on a 2GHz Pentium 4 for signing. We propose a first hardware architecture which allows to sign a document in 0.86 second on an XCV300E-7 FPGA, hence making the algorithm practical.
Document Type: report
File Description: 2+8p; 314955 bytes; 23 bytes; application/pdf; application/octet-stream
Language: English
Relation: LIP-RR - 2004-14; http://hdl.handle.net/2332/1006
Availability: http://hdl.handle.net/2332/1006
Rights: http://lara.inist.fr/utilisation.jsp
Accession Number: edsbas.64AF7DCF
Database: BASE
Description
Abstract:(eng) An algorithm producing cryptographic digital signatures less than 100 bits long with a security level matching nowadays standards has been recently proposed by Courtois, Finiasz, and Sendrier. This scheme is based on error correcting codes and consists in generating a large number of instances of a decoding problem until one of them is solved (about 9!=362880 attempts are needed). A careful software implementation requires more than one minute on a 2GHz Pentium 4 for signing. We propose a first hardware architecture which allows to sign a document in 0.86 second on an XCV300E-7 FPGA, hence making the algorithm practical.