On the trade-off between power and flexibility of FPGA clock networks
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| Title: | On the trade-off between power and flexibility of FPGA clock networks |
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| Authors: | Julien Lamoureux, Steven J. E. Wilton |
| Contributors: | The Pennsylvania State University CiteSeerX Archives |
| Source: | http://www.ece.ubc.ca/~julienl/papers/pdf/trets08.pdf. |
| Publication Year: | 2008 |
| Collection: | CiteSeerX |
| Subject Terms: | Categories and Subject Descriptors, B.7.1 [Integrated Circuits, Types and Design Styles—Gate arrays, B.7.2 [Integrated Circuits, Design Aids—Placement and routing General Terms, Algorithms, Design, Experimentation Additional Key Words and Phrases, FPGA, clock distribution networks, clock-aware placement, low-power design ACM Reference Format |
| Description: | FPGA clock networks consume a significant amount of power, since they toggle every clock cycle and must be flexible enough to implement the clocks for a wide range of different applications. The effi-ciency of FPGA clock networks can be improved by reducing this flexibility; however, reducing the flexibility introduces stricter constraints during the clustering and placement stages of the FPGA CAD flow. These constraints can reduce the overall efficiency of the final implementation. This arti-cle examines the trade-off between the power consumption and flexibility of FPGA clock networks. Specifically, this article makes three contributions. First, it presents a new parameterized clock-network framework for describing and comparing FPGA clock networks. Second, it describes new clock-aware placement techniques that are needed to find a legal placement satisfying the con-straints imposed by the clock network. Finally, it performs an empirical study to examine the trade-off between the power consumption of the clock network and the impact of the CAD con-straints for a number of different clock networks with varying amounts of flexibility. The results show that the techniques used to produce a legal placement can have a significant influence on power and the ability of the placer to find a legal solution. On average, circuits placed using the most effective techniques dissipate 5 % less overall energy and are significantly more |
| Document Type: | text |
| File Description: | application/pdf |
| Language: | English |
| Relation: | http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.628.3331; http://www.ece.ubc.ca/~julienl/papers/pdf/trets08.pdf |
| Availability: | http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.628.3331 http://www.ece.ubc.ca/~julienl/papers/pdf/trets08.pdf |
| Rights: | Metadata may be used without restrictions as long as the oai identifier remains attached to it. |
| Accession Number: | edsbas.5E3E00C7 |
| Database: | BASE |
Nájsť tento článok vo Web of Science | Abstract: | FPGA clock networks consume a significant amount of power, since they toggle every clock cycle and must be flexible enough to implement the clocks for a wide range of different applications. The effi-ciency of FPGA clock networks can be improved by reducing this flexibility; however, reducing the flexibility introduces stricter constraints during the clustering and placement stages of the FPGA CAD flow. These constraints can reduce the overall efficiency of the final implementation. This arti-cle examines the trade-off between the power consumption and flexibility of FPGA clock networks. Specifically, this article makes three contributions. First, it presents a new parameterized clock-network framework for describing and comparing FPGA clock networks. Second, it describes new clock-aware placement techniques that are needed to find a legal placement satisfying the con-straints imposed by the clock network. Finally, it performs an empirical study to examine the trade-off between the power consumption of the clock network and the impact of the CAD con-straints for a number of different clock networks with varying amounts of flexibility. The results show that the techniques used to produce a legal placement can have a significant influence on power and the ability of the placer to find a legal solution. On average, circuits placed using the most effective techniques dissipate 5 % less overall energy and are significantly more |
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