The Design and Process Reliability Analysis of Millimeter Wave CMOS Power Amplifier with a Cold Mode MOSFET Linearization
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| Názov: | The Design and Process Reliability Analysis of Millimeter Wave CMOS Power Amplifier with a Cold Mode MOSFET Linearization |
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| Autori: | N. A. Quadir, Amit Jain, S. Kashfi, Lutfi Albasha, Nasser Qaddoumi |
| Zdroj: | IET Circuits, Devices and Systems, Vol 2023 (2023) |
| Informácie o vydavateľovi: | Hindawi-IET |
| Rok vydania: | 2023 |
| Zbierka: | Directory of Open Access Journals: DOAJ Articles |
| Predmety: | Computer engineering. Computer hardware, TK7885-7895 |
| Popis: | A power amplifier design operating at 28 GHz for communication applications is presented in this paper. Analog predistorted technique is used to improve the linearity using a cold mode MOSFET linearizer. The paper reports +19.8 dBm of peak power at the output and power-added efficiency (PAE) of 17% is attained by the designed circuit. The 1-dB compression point linearity was +18.6 dBm. The adjacent channel power ratio (ACPR) simulations were performed for the different communication standards like 802_11n_40M, CDMA, IS-95, and 802_11n_20M. Design specification variations of the amplifier have been analyzed over five process corners and simulations were performed to validate compliance with standards and robustness of the designed circuit. Monte Carlo simulation were performed to assess the performance over statistical variability of PAE and power gain. It is believed that this linearization design and the verifications used are done for the first time on a 65-nm RFCMOS process. |
| Druh dokumentu: | article in journal/newspaper |
| Jazyk: | English |
| Relation: | http://dx.doi.org/10.1049/2023/2265697; https://doaj.org/toc/1751-8598; https://doaj.org/article/d3d0af109b684a16bd14110621c9cfae |
| DOI: | 10.1049/2023/2265697 |
| Dostupnosť: | https://doi.org/10.1049/2023/2265697 https://doaj.org/article/d3d0af109b684a16bd14110621c9cfae |
| Prístupové číslo: | edsbas.52CA4BFE |
| Databáza: | BASE |
Nájsť tento článok vo Web of Science | Abstrakt: | A power amplifier design operating at 28 GHz for communication applications is presented in this paper. Analog predistorted technique is used to improve the linearity using a cold mode MOSFET linearizer. The paper reports +19.8 dBm of peak power at the output and power-added efficiency (PAE) of 17% is attained by the designed circuit. The 1-dB compression point linearity was +18.6 dBm. The adjacent channel power ratio (ACPR) simulations were performed for the different communication standards like 802_11n_40M, CDMA, IS-95, and 802_11n_20M. Design specification variations of the amplifier have been analyzed over five process corners and simulations were performed to validate compliance with standards and robustness of the designed circuit. Monte Carlo simulation were performed to assess the performance over statistical variability of PAE and power gain. It is believed that this linearization design and the verifications used are done for the first time on a 65-nm RFCMOS process. |
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| DOI: | 10.1049/2023/2265697 |