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A Power-Efficient Configurable Low-Complexity MIMO Detector

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Bibliographic Details
Title: A Power-Efficient Configurable Low-Complexity MIMO Detector
Authors: Huang, Chien-Jen, Yu, Chung-Wen, Ma, Hsi-Pin
Contributors: 馬席彬
Publisher Information: Institute of Electrical and Electronics Engineers
Publication Year: 2009
Collection: National Tsing Hua University Institutional Repository (NTHUR)
Subject Terms: SPACE-TIME CODES, SPHERE-DECODING ALGORITHM, WIRELESS LANS, IMPLEMENTATION
Time: 45
Description: 2030124010005 ; 電機工程學系 ; In this paper, we propose a power-efficient configurable multiple-input-multiple-output (MIMO) detector, supporting QPSK, 16-QAM, and 64-QAM with low complexity. The approach divides a large MIMO detector into two subsystems: a core detector and a residual detector. The core detector, a low-cost 2 x 2 V-BLAST with ML detector, is used to detect the first two significant outputs. This detector not only efficiently increases the reliability of the entire MIMO detector through its ML performance in mitigating error propagation but also reduces the computational complexity by its search space reduction capability to decrease the computation from O(C-2) to O(C) (C is the constellation size). The residual detector is an ordered successive interference cancellation (OSIC) detector that detects the rest outputs. The results of bit-error-rate simulations demonstrate that the proposed detector significantly outperforms the OSIC detector. Furthermore, two complete ASIC implementations fabricated by 0.13-mu m 1P8M CMOS technology are presented. We show that the proposed detector, which is configurable from 2 x 2 to 6 x 4 MIMO configurations, has the lowest complexity compared to other fabricated works with 64-QAM demodulation. Moreover, the measured normalized power efficiency of 3.8 Mb/s/mW is shown to be the most power-efficient design compared with the designs of other fabricated works.
Document Type: journal/newspaper
Language: English
ISSN: 1549-8328
Relation: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, IEEE, Volume 56, Issue 2, FEB 2009, Pages 485-496; http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/72081
Availability: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/72081
Accession Number: edsbas.44272B01
Database: BASE
Description
Abstract:2030124010005 ; 電機工程學系 ; In this paper, we propose a power-efficient configurable multiple-input-multiple-output (MIMO) detector, supporting QPSK, 16-QAM, and 64-QAM with low complexity. The approach divides a large MIMO detector into two subsystems: a core detector and a residual detector. The core detector, a low-cost 2 x 2 V-BLAST with ML detector, is used to detect the first two significant outputs. This detector not only efficiently increases the reliability of the entire MIMO detector through its ML performance in mitigating error propagation but also reduces the computational complexity by its search space reduction capability to decrease the computation from O(C-2) to O(C) (C is the constellation size). The residual detector is an ordered successive interference cancellation (OSIC) detector that detects the rest outputs. The results of bit-error-rate simulations demonstrate that the proposed detector significantly outperforms the OSIC detector. Furthermore, two complete ASIC implementations fabricated by 0.13-mu m 1P8M CMOS technology are presented. We show that the proposed detector, which is configurable from 2 x 2 to 6 x 4 MIMO configurations, has the lowest complexity compared to other fabricated works with 64-QAM demodulation. Moreover, the measured normalized power efficiency of 3.8 Mb/s/mW is shown to be the most power-efficient design compared with the designs of other fabricated works.
ISSN:15498328