A 2.2 GOPS video DSP with 2-RISC MIMD, 6-PE SIMD architecture for real-time MPEG2 video coding/decoding
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| Title: | A 2.2 GOPS video DSP with 2-RISC MIMD, 6-PE SIMD architecture for real-time MPEG2 video coding/decoding |
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| Authors: | Iwata, E., Seno, K., Aikawa, M., Ohki, M., Yoshikawa, H., Fukuzawa, Y., Hanaki, H., Nishibori, K., Kondo, Y., Takamuki, H., Nagai, T., Hasegawa, K., Okuda, H., Kumata, I., Soneda, M., Iwase, S., Yamazaki, T. |
| Source: | 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers ; page 258-259 |
| Publisher Information: | IEEE |
| Publication Year: | 2002 |
| Document Type: | conference object |
| Language: | unknown |
| DOI: | 10.1109/isscc.1997.585378 |
| Availability: | https://doi.org/10.1109/isscc.1997.585378 http://xplorestaging.ieee.org/ielx3/4459/12641/00585378.pdf?arnumber=585378 |
| Accession Number: | edsbas.437ED226 |
| Database: | BASE |
Nájsť tento článok vo Web of Science | DOI: | 10.1109/isscc.1997.585378 |
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