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Supporting task creation inside FPGA devices

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Bibliographic Details
Title: Supporting task creation inside FPGA devices
Authors: Bosch Pons, Jaume, Álvarez Martínez, Carlos, Jiménez González, Daniel
Publisher Information: Barcelona Supercomputing Center
Publication Year: 2019
Collection: Universitat Politècnica de Catalunya, BarcelonaTech: UPCommons - Global access to UPC knowledge
Subject Terms: Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, High performance computing, Heterogeneous computing, Device offloading, Task based parallel programming models, High-performance computing, Càlcul intensiu (Informàtica), Computació heterogènia
Description: The most common model to use co-processors/accelerators is the master-slave model where the slaves (coprocessors/ accelerators) are driven by a general purpose cpu. This simplifies the management of the accelerators because they cannot actively interact with the runtime and they are just passive slaves that operate over the memory under demand. However, the master-slave model limits system possibilities and introduces synchronization overheads that could be avoided. To overcome those limitations and increase the possibilities of accelerators, we propose extending task based programming models (like OpenMP [1] or OmpSs) to support some runtime APIs inside the FPGA co-processor. As a proof-of-concept, we implemented our proposal over the OmpSs@FPGA environment [2] adding the needed infrastructure in the FPGA bitstream and modifying the existing tools to support creation of children tasks inside a task offloaded to an FPGA accelerator. In addition, we added support to synchronize the children tasks created by a FPGA task regardless they are executed in a SMP host thread or they also target another FPGA accelerator in the same co-processor.
Document Type: conference object
File Description: 2 p.; application/pdf
Language: English
Relation: http://hdl.handle.net/2117/166955
Availability: http://hdl.handle.net/2117/166955
Rights: Attribution-NonCommercial-NoDerivs 3.0 Spain ; http://creativecommons.org/licenses/by-nc-nd/3.0/es/ ; Open Access
Accession Number: edsbas.31F9C17C
Database: BASE
Description
Abstract:The most common model to use co-processors/accelerators is the master-slave model where the slaves (coprocessors/ accelerators) are driven by a general purpose cpu. This simplifies the management of the accelerators because they cannot actively interact with the runtime and they are just passive slaves that operate over the memory under demand. However, the master-slave model limits system possibilities and introduces synchronization overheads that could be avoided. To overcome those limitations and increase the possibilities of accelerators, we propose extending task based programming models (like OpenMP [1] or OmpSs) to support some runtime APIs inside the FPGA co-processor. As a proof-of-concept, we implemented our proposal over the OmpSs@FPGA environment [2] adding the needed infrastructure in the FPGA bitstream and modifying the existing tools to support creation of children tasks inside a task offloaded to an FPGA accelerator. In addition, we added support to synchronize the children tasks created by a FPGA task regardless they are executed in a SMP host thread or they also target another FPGA accelerator in the same co-processor.