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A RISC-V SystemC-TLM simulator

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Bibliographic Details
Title:	A RISC-V SystemC-TLM simulator
Authors:	Màrius
Publisher Information:	Zenodo
Publication Year:	2020
Collection:	Zenodo
Subject Terms:	risc-v, SystemC, TLM-2.0, Simulation Infrastructure, ISS
Description:	This work presents a SystemC-TLM based simulator for a RISC-V microcontroller. This simulator is focused on simplicity and easy expandable of a RISC-V. It is built around a full RISC-V instruction set simulator that supports full RISC-V ISA and extensions M, A, C, Zicsr and Zifencei. The ISS is encapsulated in a TLM-2 wrapper that enables it to communicate with any other TLM-2 compatible module. The simulator also includes a very basic set of peripherals to enable a complete SoC simulator. The running code can be compiled with standard tools and using standard C libraries without modifications.
Document Type:	conference object
Language:	English
Relation:	https://zenodo.org/records/7181526; oai:zenodo.org:7181526; https://doi.org/10.5281/zenodo.7181526
DOI:	10.5281/zenodo.7181526
Availability:	https://doi.org/10.5281/zenodo.7181526 https://zenodo.org/records/7181526
Rights:	Creative Commons Attribution 4.0 International ; cc-by-4.0 ; https://creativecommons.org/licenses/by/4.0/legalcode
Accession Number:	edsbas.2B1DC4C6
Database:	BASE

Description
Abstract:	This work presents a SystemC-TLM based simulator for a RISC-V microcontroller. This simulator is focused on simplicity and easy expandable of a RISC-V. It is built around a full RISC-V instruction set simulator that supports full RISC-V ISA and extensions M, A, C, Zicsr and Zifencei. The ISS is encapsulated in a TLM-2 wrapper that enables it to communicate with any other TLM-2 compatible module. The simulator also includes a very basic set of peripherals to enable a complete SoC simulator. The running code can be compiled with standard tools and using standard C libraries without modifications.
DOI:	10.5281/zenodo.7181526