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Specialized Scalar and SIMD Instructions for Error Correction Codes Decoding on RISC-V Processors

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Titel: Specialized Scalar and SIMD Instructions for Error Correction Codes Decoding on RISC-V Processors
Autoren: Mael Tourres, Cyrille Chavet, Bertrand Le Gal, Philippe Coussy
Weitere Verfasser: Chavet, Cyrille, Laboratoire de l'intégration, du matériau au système (IMS), Université Sciences et Technologies - Bordeaux 1 (UB)-Institut Polytechnique de Bordeaux-Centre National de la Recherche Scientifique (CNRS), Equipe Hardware ARchitectures and CAD tools (Lab-STICC_ARCAD), Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC), École Nationale d'Ingénieurs de Brest (ENIB)-Université de Bretagne Sud (UBS)-Université de Brest (UBO)-École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne)-Institut Mines-Télécom Paris (IMT)-Centre National de la Recherche Scientifique (CNRS)-Université Bretagne Loire (UBL)-IMT Atlantique (IMT Atlantique), Institut Mines-Télécom Paris (IMT)-École Nationale d'Ingénieurs de Brest (ENIB)-Université de Bretagne Sud (UBS)-Université de Brest (UBO)-École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne)-Institut Mines-Télécom Paris (IMT)-Centre National de la Recherche Scientifique (CNRS)-Université Bretagne Loire (UBL)-IMT Atlantique (IMT Atlantique), Institut Mines-Télécom Paris (IMT), Architectures and Methods for Resilient Systems (TIMA-AMfoRS), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP), Université Grenoble Alpes (UGA), Architectures matérielles spécialisées pour l’ère post loi-de-Moore (TARAN), Centre Inria de l'Université de Rennes, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-ARCHITECTURE (IRISA-D3), Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique), Institut Mines-Télécom Paris (IMT)-Institut Mines-Télécom Paris (IMT)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut Mines-Télécom Paris (IMT)-Institut Mines-Télécom Paris (IMT)-Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique), Institut Mines-Télécom Paris (IMT)-Institut Mines-Télécom Paris (IMT), Université de Bretagne Sud (UBS), PEC bretagne
Quelle: IEEE Access, Vol 13, Pp 6964-6976 (2025)
Verlagsinformationen: Institute of Electrical and Electronics Engineers (IEEE), 2025.
Publikationsjahr: 2025
Schlagwörter: [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-TS] Computer Science [cs]/Signal and Image Processing, [INFO.INFO-NE] Computer Science [cs]/Neural and Evolutionary Computing [cs.NE], RISC-V, [INFO.INFO-IA]Computer Science [cs]/Computer Aided Engineering, [INFO.INFO-NE]Computer Science [cs]/Neural and Evolutionary Computing [cs.NE], [INFO.INFO-IA] Computer Science [cs]/Computer Aided Engineering, SIMD, [INFO.INFO-ES] Computer Science [cs]/Embedded Systems, TK1-9971, ASIP, [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, 4G, IoT devices, Electrical engineering. Electronics. Nuclear engineering, 5G, forward error correction codes
Beschreibung: The rapid deployment of Internet-of-Things (IoT) devices for a few years has been impressive, and the progressive deployment of 5G will accelerate things even further. Indeed, this standard opens the door to a new generation of standards aimed at a convergence of networks and communication protocols (WiFi, LTE, 4G etc.). This results in the need for flexible implementations of different families of codes, such as, LPDC, NB-LDPC, turbo codes and polar codes. In this context, the work presented in this article proposes the design of a flexible instruction set processor for an IoT context. The objective is to improve the performance level of low-complexity processor cores through instruction set extensions for Error Correction Code (ECC) decoding. The approach discussed is supported by experimental results obtained based on a RISC-V architecture to which specific instruction sets have been added. The results demonstrate a reduction in the required processing clock cycles up to 44.1% for polar codes, 39.2% for LDPC codes, 21.8% for NB-LDPC codes, and 24.3% for turbo codes (4G LTE) codes with a classical Single Instruction Single Data (SISD) approach. Moreover, Single Instruction Multiple Data (SIMD) parallelization strategy enables execution time savings that are far more impressive. The number of clock cycles required to decode a data bit is reduced by 65.6% to 76.9%, with a limited hardware over-cost from 0.6% to 34% (depending on the error correction code family and the targeted RISC-V core).
Publikationsart: Article
Dateibeschreibung: application/pdf
ISSN: 2169-3536
DOI: 10.1109/access.2025.3527028
Zugangs-URL: https://doaj.org/article/958c7c350e714b80a6138fdc919bd82d
Rights: CC BY
CC BY NC
Dokumentencode: edsair.doi.dedup.....fab68e29c6d9598de24569f1e3e42baa
Datenbank: OpenAIRE
Beschreibung
Abstract:The rapid deployment of Internet-of-Things (IoT) devices for a few years has been impressive, and the progressive deployment of 5G will accelerate things even further. Indeed, this standard opens the door to a new generation of standards aimed at a convergence of networks and communication protocols (WiFi, LTE, 4G etc.). This results in the need for flexible implementations of different families of codes, such as, LPDC, NB-LDPC, turbo codes and polar codes. In this context, the work presented in this article proposes the design of a flexible instruction set processor for an IoT context. The objective is to improve the performance level of low-complexity processor cores through instruction set extensions for Error Correction Code (ECC) decoding. The approach discussed is supported by experimental results obtained based on a RISC-V architecture to which specific instruction sets have been added. The results demonstrate a reduction in the required processing clock cycles up to 44.1% for polar codes, 39.2% for LDPC codes, 21.8% for NB-LDPC codes, and 24.3% for turbo codes (4G LTE) codes with a classical Single Instruction Single Data (SISD) approach. Moreover, Single Instruction Multiple Data (SIMD) parallelization strategy enables execution time savings that are far more impressive. The number of clock cycles required to decode a data bit is reduced by 65.6% to 76.9%, with a limited hardware over-cost from 0.6% to 34% (depending on the error correction code family and the targeted RISC-V core).
ISSN:21693536
DOI:10.1109/access.2025.3527028