Hybrid Logic Locking Using Horned Lizard Optimization and Q-Learning for Secure Hardware Design
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| Názov: | Hybrid Logic Locking Using Horned Lizard Optimization and Q-Learning for Secure Hardware Design |
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| Autori: | S., Karthik, C., Sujatha, M., Premkumar |
| Zdroj: | Tehnicki vjesnik - Technical Gazette. 32 |
| Informácie o vydavateľovi: | University of Slavonski Brod, Mechanical Engineering Faculty in Slavonski Brod, 2025. |
| Rok vydania: | 2025 |
| Predmety: | logic locking, intellectual property protection, hardware security, horned lizard optimization, Q-Learning |
| Popis: | Logic locking has become an essential technique for safeguarding intellectual property (IP) in hardware designs against reverse engineering and tampering. However, existing methods often rely on the random insertion of key gates in original circuits, neglecting critical factors such as area overhead and output corruption rates. This paper presents a novel hybrid logic locking technique aimed at maximizing security while minimizing the overhead of key gate insertion. The proposed method integrates the Horned Lizard Optimization (HLO), a metaheuristic inspired by the adaptive defense strategies of horned lizards, with a Q-learning model. The Q-learning component enhances the exploration stage of HLO, enabling the optimal selection of insertion points for key gates in the circuit. Experimental evaluations on benchmark circuits demonstrate that the proposed technique achieves an average area, delay, and power overhead of 16.85%, 0.0475%, and 2.3345%, respectively, outperforming state-of-the-art methods in terms of efficiency and security. |
| Druh dokumentu: | Article |
| Popis súboru: | application/pdf |
| ISSN: | 1848-6339 1330-3651 |
| DOI: | 10.17559/tv-20241227002215 |
| Prístupové číslo: | edsair.doi.dedup.....c6a8eb5e597e754d238d410f256ee6b5 |
| Databáza: | OpenAIRE |
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Nájsť tento článok vo Web of Science | Abstrakt: | Logic locking has become an essential technique for safeguarding intellectual property (IP) in hardware designs against reverse engineering and tampering. However, existing methods often rely on the random insertion of key gates in original circuits, neglecting critical factors such as area overhead and output corruption rates. This paper presents a novel hybrid logic locking technique aimed at maximizing security while minimizing the overhead of key gate insertion. The proposed method integrates the Horned Lizard Optimization (HLO), a metaheuristic inspired by the adaptive defense strategies of horned lizards, with a Q-learning model. The Q-learning component enhances the exploration stage of HLO, enabling the optimal selection of insertion points for key gates in the circuit. Experimental evaluations on benchmark circuits demonstrate that the proposed technique achieves an average area, delay, and power overhead of 16.85%, 0.0475%, and 2.3345%, respectively, outperforming state-of-the-art methods in terms of efficiency and security. |
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| ISSN: | 18486339 13303651 |
| DOI: | 10.17559/tv-20241227002215 |