A 15-nA quiescent current capacitor-less LDO for sub-1V μW-powered fully-harvested systems
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| Title: | A 15-nA quiescent current capacitor-less LDO for sub-1V μW-powered fully-harvested systems |
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| Authors: | Privitera M., Ballo A., Grasso A. D., Alioto M. |
| Source: | 2024 IEEE International Symposium on Circuits and Systems (ISCAS) |
| Publisher Information: | IEEE, 2024. |
| Publication Year: | 2024 |
| Subject Terms: | Low drop-out (LDO) voltage regulator, IoT, Energy harvesting |
| Description: | This work proposes a very-low quiescent current corner-compensated analog LDO with reconfigurable topology for multiple output voltage values, and its pW-powered voltage reference. The design of the proposed LDO has been optimized for sub-1V for battery-less systems that exhibit an average power consumption from hundreds nW up to hundreds of μW. Measurement results on a 180nm standard CMOS technology prove the effectiveness of the design strategy and validate the working principle of the LDO. The proposed analog LDO can work with a supply voltage down to 0.55-0.6V, consuming only 15-nA of quiescent current and it shows 6.4x lower FoMt (7.5x for FoMtv) compared with similar prior art. |
| Document Type: | Article Conference object |
| File Description: | application/pdf |
| DOI: | 10.1109/iscas58744.2024.10558388 |
| Access URL: | https://hdl.handle.net/20.500.11769/627731 https://doi.org/10.1109/ISCAS58744.2024.10558388 |
| Rights: | STM Policy #29 |
| Accession Number: | edsair.doi.dedup.....95b3ecbd2ba5205cc735dd68f0cd699a |
| Database: | OpenAIRE |
Nájsť tento článok vo Web of Science | Abstract: | This work proposes a very-low quiescent current corner-compensated analog LDO with reconfigurable topology for multiple output voltage values, and its pW-powered voltage reference. The design of the proposed LDO has been optimized for sub-1V for battery-less systems that exhibit an average power consumption from hundreds nW up to hundreds of μW. Measurement results on a 180nm standard CMOS technology prove the effectiveness of the design strategy and validate the working principle of the LDO. The proposed analog LDO can work with a supply voltage down to 0.55-0.6V, consuming only 15-nA of quiescent current and it shows 6.4x lower FoMt (7.5x for FoMtv) compared with similar prior art. |
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| DOI: | 10.1109/iscas58744.2024.10558388 |