Low-power SiPM readout BETA ASIC for space applications

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Bibliographic Details
Title: Low-power SiPM readout BETA ASIC for space applications
Authors: Sanmukh, Anand, Gómez, Sergio, Comerma, Albert, Mauricio, Joan, Manera, Rafael, Sanuy, Andreu, Guberman, Daniel, Catala, Roger, Espinya, Albert, Orta, Marina, Torre, Oscar de la, Gascón, David, HERD collaboration
Contributors: Conferencia de Rectores de las Universidades Españolas, Consejo Superior de Investigaciones Científicas (España), Ministerio de Ciencia e Innovación (España), Agencia Estatal de Investigación (España), Ministerio de Ciencia, Innovación y Universidades (España), European Commission, Universitat Politècnica de Catalunya. Departament d'Enginyeria Minera, Industrial i TIC, Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica, Universitat Politècnica de Catalunya. RIIS - Grup de Recerca en Recursos i Indústries Intel·ligents i Sostenibles
Source: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Articles publicats en revistes (Física Quàntica i Astrofísica)
Dipòsit Digital de la UB
Universidad de Barcelona
Digital.CSIC. Repositorio Institucional del CSIC
Consejo Superior de Investigaciones Científicas (CSIC)
Publisher Information: Springer Science and Business Media LLC, 2024.
Publication Year: 2024
Subject Terms: Silicon, Mixed-mode ASICs, Circuits integrats analògics, Electronic circuit design, Space technology, Silicon photomultipliers, Front-end electronics, Integrated circuits, Detectors, Photon sensors, 7. Clean energy, 01 natural sciences, Disseny de circuits electrònics, Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Processament del senyal, Radiation detectors, Silici, Àrees temàtiques de la UPC::Enginyeria electrònica::Instrumentació i mesura::Sensors i actuadors, 0103 physical sciences, Circuits integrats, Analog integrated circuits
Description: The BETA application-specific integrated circuit (ASIC) is a fully programmable chip designed to amplify, shape and digitize the signal of up to 64 Silicon photomultiplier (SiPM) channels, with a power consumption of approximately $$\sim$$ ∼ 1 mW/channel. Owing to its dual-path gain, the BETA chip is capable of resolving single photoelectrons (phes) with a signal-to-noise ratio (SNR) >5 while simultaneously achieving a dynamic range of $$\sim$$ ∼ 4000 phes. Thus, BETA can provide a cost-effective solution for the readout of SiPMs in space missions and other applications with a maximum rate below 10 kHz. In this study, we describe the key characteristics of the BETA ASIC and present an evaluation of the performance of its 16-channel version, which is implemented using 130 nm technology. The ASIC also contains two discriminators that can provide trigger signals with a time jitter down to 400 ps FWHM for 10 phes. The linearity error of the charge gain measurement was less than 2% for a dynamic range as large as 15 bits.
Document Type: Article
File Description: application/pdf
Language: English
ISSN: 2210-3147
1001-8042
DOI: 10.1007/s41365-024-01419-z
DOI: 10.13039/501100000780
DOI: 10.13039/501100004837
DOI: 10.13039/501100003339
DOI: 10.13039/501100011033
Access URL: https://hdl.handle.net/2445/216277
http://hdl.handle.net/10261/365692
https://hdl.handle.net/2117/408197
https://doi.org/10.1007/s41365-024-01419-z
http://hdl.handle.net/2445/216277
Rights: CC BY
Accession Number: edsair.doi.dedup.....39573dda3a28439a09841e9fc93244e3
Database: OpenAIRE
Description
Abstract:The BETA application-specific integrated circuit (ASIC) is a fully programmable chip designed to amplify, shape and digitize the signal of up to 64 Silicon photomultiplier (SiPM) channels, with a power consumption of approximately $$\sim$$ ∼ 1 mW/channel. Owing to its dual-path gain, the BETA chip is capable of resolving single photoelectrons (phes) with a signal-to-noise ratio (SNR) >5 while simultaneously achieving a dynamic range of $$\sim$$ ∼ 4000 phes. Thus, BETA can provide a cost-effective solution for the readout of SiPMs in space missions and other applications with a maximum rate below 10 kHz. In this study, we describe the key characteristics of the BETA ASIC and present an evaluation of the performance of its 16-channel version, which is implemented using 130 nm technology. The ASIC also contains two discriminators that can provide trigger signals with a time jitter down to 400 ps FWHM for 10 phes. The linearity error of the charge gain measurement was less than 2% for a dynamic range as large as 15 bits.
ISSN:22103147
10018042
DOI:10.1007/s41365-024-01419-z