Detecting Hardware Trojans in Microprocessors via Hardware Error Correction Code-based Modules
Uložené v:
| Názov: | Detecting Hardware Trojans in Microprocessors via Hardware Error Correction Code-based Modules |
|---|---|
| Autori: | Palumbo, Alessandro, Salvador, Ruben |
| Prispievatelia: | Palumbo, Alessandro |
| Zdroj: | 2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS). :1-7 |
| Publication Status: | Preprint |
| Informácie o vydavateľovi: | IEEE, 2025. |
| Rok vydania: | 2025 |
| Predmety: | FOS: Computer and information sciences, Cryptography and Security, Hardware Trojans, Hardware Security, RISC-V, Error Correction Codes, Cryptography and Security (cs.CR), Microprocessor-based System, [INFO.INFO-CR] Computer Science [cs]/Cryptography and Security [cs.CR] |
| Popis: | Software-exploitable Hardware Trojans (HTs) enable attackers to execute unauthorized software or gain illicit access to privileged operations. This manuscript introduces a hardware-based methodology for detecting runtime HT activations using Error Correction Codes (ECCs) on a RISC-V microprocessor. Specifically, it focuses on HTs that inject malicious instructions, disrupting the normal execution flow by triggering unauthorized programs. To counter this threat, the manuscript introduces a Hardware Security Checker (HSC) leveraging Hamming Single Error Correction (HSEC) architectures for effective HT detection. Experimental results demonstrate that the proposed solution achieves a 100% detection rate for potential HT activations, with no false positives or undetected attacks. The implementation incurs minimal overhead, requiring only 72 #LUTs, 24 #FFs, and 0.5 #BRAM while maintaining the microprocessor's original operating frequency and introducing no additional time delay. To appear at the 31st IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) 2025, 7 pages, 5 figures |
| Druh dokumentu: | Article Conference object |
| Popis súboru: | application/pdf |
| DOI: | 10.1109/iolts65288.2025.11116960 |
| DOI: | 10.48550/arxiv.2506.15417 |
| Prístupová URL adresa: | http://arxiv.org/abs/2506.15417 |
| Rights: | STM Policy #29 arXiv Non-Exclusive Distribution CC BY |
| Prístupové číslo: | edsair.doi.dedup.....265a1e1de3fec57e4ff409606530b83f |
| Databáza: | OpenAIRE |
Nájsť tento článok vo Web of Science | Abstrakt: | Software-exploitable Hardware Trojans (HTs) enable attackers to execute unauthorized software or gain illicit access to privileged operations. This manuscript introduces a hardware-based methodology for detecting runtime HT activations using Error Correction Codes (ECCs) on a RISC-V microprocessor. Specifically, it focuses on HTs that inject malicious instructions, disrupting the normal execution flow by triggering unauthorized programs. To counter this threat, the manuscript introduces a Hardware Security Checker (HSC) leveraging Hamming Single Error Correction (HSEC) architectures for effective HT detection. Experimental results demonstrate that the proposed solution achieves a 100% detection rate for potential HT activations, with no false positives or undetected attacks. The implementation incurs minimal overhead, requiring only 72 #LUTs, 24 #FFs, and 0.5 #BRAM while maintaining the microprocessor's original operating frequency and introducing no additional time delay.<br />To appear at the 31st IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) 2025, 7 pages, 5 figures |
|---|---|
| DOI: | 10.1109/iolts65288.2025.11116960 |