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FPGA implementation of normalized correlation function

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Bibliographic Details
Title: FPGA implementation of normalized correlation function
Authors: Krzysztof Mroczek
Source: International Journal of Electronics and Telecommunications, Vol vol. 71, Iss No 3, Pp 1-8 (2025)
Publisher Information: Polish Academy of Sciences Chancellery, 2025.
Publication Year: 2025
Subject Terms: hardware algorithms, correlation, time series analysis, pulse recognition, Telecommunication, embedded systems, Electrical engineering. Electronics. Nuclear engineering, TK5101-6720, fpga, TK1-9971
Description: Correlation analysis is a frequently used tool in signal detection and classification tasks. This paper presents the design and FPGA implementations of a hardware module for calculating the Pearson correlation coefficient. This module is designed for use in signal template matching, where a measurement signal is correlated with a template. It has been described in Verilog and implemented on Intel Cyclone V FPGA. The module consists of two main parts, which are: a correlation filter and normalization modules. Correlation filters performing the calculation in the time domain and in the frequency domain are described. The project has been verified in simulation using ModelSim and checked on hardware. As a result of this work, hardware IP cores are developed enabling parametrization and programming in data word-lengths, filter size, calculation speed, FFT/IFFT size, length, and number of processing templates. Developed resources are intended to be used in FPGA-based hardware, e.g. DAQ systems, working with sampling frequencies from kHz to above 130 MHz.
Document Type: Article
Language: Polish
ISSN: 2300-1933
2081-8491
DOI: 10.24425/ijet.2025.153627
Access URL: https://doaj.org/article/13d79d1846dc4621ae079157b80e12b9
https://doi.org/10.24425/ijet.2025.153627
Accession Number: edsair.doi.dedup.....12d521464b1e024a705e9a64bb418318
Database: OpenAIRE
Description
Abstract:Correlation analysis is a frequently used tool in signal detection and classification tasks. This paper presents the design and FPGA implementations of a hardware module for calculating the Pearson correlation coefficient. This module is designed for use in signal template matching, where a measurement signal is correlated with a template. It has been described in Verilog and implemented on Intel Cyclone V FPGA. The module consists of two main parts, which are: a correlation filter and normalization modules. Correlation filters performing the calculation in the time domain and in the frequency domain are described. The project has been verified in simulation using ModelSim and checked on hardware. As a result of this work, hardware IP cores are developed enabling parametrization and programming in data word-lengths, filter size, calculation speed, FFT/IFFT size, length, and number of processing templates. Developed resources are intended to be used in FPGA-based hardware, e.g. DAQ systems, working with sampling frequencies from kHz to above 130 MHz.
ISSN:23001933
20818491
DOI:10.24425/ijet.2025.153627