A Multi-Bit PUF Architecture Using a 2T Sub-Threshold Voltage Divider
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| Title: | A Multi-Bit PUF Architecture Using a 2T Sub-Threshold Voltage Divider |
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| Authors: | Vatalaro M., De Rose R., Maccaronio V., Lanuzza M., Crupi F. |
| Source: | 2025 IEEE International Symposium on Circuits and Systems (ISCAS). :1-5 |
| Publisher Information: | IEEE, 2025. |
| Publication Year: | 2025 |
| Subject Terms: | multi-bit, sub-threshold voltage divider, SMV, hardware security, PUF |
| Description: | In this paper, a highly reliable multi-bit physically unclonable function (PUF) is proposed. The solution relies on an already tested two-transistor (2T) sub-threshold voltage divider as core circuit along with a multi-bit architecture able to carry out two highly stable bits from three bits generated by a proper entropy quantization. Twenty measured samples of the bitcell core were used to fit a customized Verilog-A model, which was then imported into Cadence Virtuoso environment for the architecture-level analysis. The proposed solution was tested across Monte Carlo simulations at both golden key (GK) and different environmental conditions, while also including the effect of noise. Simulation results prove the effectiveness in generating two highly stable bits for each cell after spatial majority voting and best stability selection. Indeed, no instability was observed in the 0-50 °C temperature range for the two output bits. |
| Document Type: | Article Conference object |
| DOI: | 10.1109/iscas56072.2025.11044271 |
| Access URL: | https://hdl.handle.net/20.500.11770/387402 https://doi.org/10.1109/ISCAS56072.2025.11044271 |
| Rights: | STM Policy #29 |
| Accession Number: | edsair.doi.dedup.....0393238d4f290cbaf1a66df88590a057 |
| Database: | OpenAIRE |
Nájsť tento článok vo Web of Science | Abstract: | In this paper, a highly reliable multi-bit physically unclonable function (PUF) is proposed. The solution relies on an already tested two-transistor (2T) sub-threshold voltage divider as core circuit along with a multi-bit architecture able to carry out two highly stable bits from three bits generated by a proper entropy quantization. Twenty measured samples of the bitcell core were used to fit a customized Verilog-A model, which was then imported into Cadence Virtuoso environment for the architecture-level analysis. The proposed solution was tested across Monte Carlo simulations at both golden key (GK) and different environmental conditions, while also including the effect of noise. Simulation results prove the effectiveness in generating two highly stable bits for each cell after spatial majority voting and best stability selection. Indeed, no instability was observed in the 0-50 °C temperature range for the two output bits. |
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| DOI: | 10.1109/iscas56072.2025.11044271 |