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Parallel architecture for high-speed LZSS data coding/decoding.

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Titel: Parallel architecture for high-speed LZSS data coding/decoding.
Autoren: Fujioka, Toyota1, Aso, Hirotomo2
Quelle: Systems & Computers in Japan. 8/1/2000, Vol. 31 Issue 9, p49-59. 11p.
Schlagwörter: Data compression, Parallel computers, Computer architecture, Computer systems, Computers, Coding theory
Abstract: Methods to transfer and store information efficiently are in demand due to developments in computer technology. Data compression technology has developed as a viable technology for data usage and is being used in various fields. One data compression method widely used at present is LZSS coding. LZSS coding is a data compression method that provides high compression ratios by eliminating the redundancies in coding expressions in LZ77 coding [4]. Speed is needed for the transfer of large amounts of data over networks, and dedicated hardware for data compression has been considered as a means to satisfy this need. In this paper the authors propose a high-speed LZSS coding and decoding parallel processing architecture, PAHL-LZSS, to achieve high-speed LZSS coding. PAHL-LZSS provides compression at a lower computational burden by actively using the statistical characteristics of generated coding and by using parallel processing architecture. Both coding and decoding are achieved in one circuit. In addition, the PAHL-LZSS architecture is described using a hardware description language, and its likely characteristics are clarified. In addition, in this paper the authors propose a packaging method using modules as a way to package PAHL-LZSS and PAHL more easily. © 2000 Scripta Technica, Syst Comp Jpn, 31(9): 49–59, 2000 [ABSTRACT FROM AUTHOR]
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Abstract:Methods to transfer and store information efficiently are in demand due to developments in computer technology. Data compression technology has developed as a viable technology for data usage and is being used in various fields. One data compression method widely used at present is LZSS coding. LZSS coding is a data compression method that provides high compression ratios by eliminating the redundancies in coding expressions in LZ77 coding [4]. Speed is needed for the transfer of large amounts of data over networks, and dedicated hardware for data compression has been considered as a means to satisfy this need. In this paper the authors propose a high-speed LZSS coding and decoding parallel processing architecture, PAHL-LZSS, to achieve high-speed LZSS coding. PAHL-LZSS provides compression at a lower computational burden by actively using the statistical characteristics of generated coding and by using parallel processing architecture. Both coding and decoding are achieved in one circuit. In addition, the PAHL-LZSS architecture is described using a hardware description language, and its likely characteristics are clarified. In addition, in this paper the authors propose a packaging method using modules as a way to package PAHL-LZSS and PAHL more easily. © 2000 Scripta Technica, Syst Comp Jpn, 31(9): 49–59, 2000 [ABSTRACT FROM AUTHOR]
ISSN:08821666
DOI:10.1002/1520-684X(200008)31:9<49::AID-SCJ6>3.0.CO;2-K