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Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey.

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Title: Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey.
Authors: Pagiamtzis, Kostas, Sheikholeslami, Ali
Source: IEEE Journal of Solid-State Circuits; Mar2006, Vol. 41 Issue 3, p712-727, 16p, 2 Black and White Photographs, 23 Diagrams, 7 Charts
Subject Terms: COMPUTER storage devices, NETWORK routers, DATA packeting, COMPUTER architecture, DETECTORS, ENERGY consumption
Abstract: We survey recent developments in the design of large-capacity content-addressable memory (CAM). A CAM is a memory that implements the lookup-table function in a single clock cycle using dedicated comparison circuitry. CAMs are especially popular in network routers for packet forwarding and packet classification, but they are also beneficial in a variety of other applications that require high-speed table lookup. The main CAM-design challenge is to reduce power consumption associated with the large amount of parallel active circuitry, without sacrificing speed or memory density. In this paper, we review CAM-design techniques at the circuit level and at the architectural level. At the circuit level, we review low-power matchline sensing techniques and searchline driving approaches. At the architectural level we review three methods for reducing power consumption. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey.
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  Data: <searchLink fieldCode="AR" term="%22Pagiamtzis%2C+Kostas%22">Pagiamtzis, Kostas</searchLink><br /><searchLink fieldCode="AR" term="%22Sheikholeslami%2C+Ali%22">Sheikholeslami, Ali</searchLink>
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  Data: IEEE Journal of Solid-State Circuits; Mar2006, Vol. 41 Issue 3, p712-727, 16p, 2 Black and White Photographs, 23 Diagrams, 7 Charts
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  Data: <searchLink fieldCode="DE" term="%22COMPUTER+storage+devices%22">COMPUTER storage devices</searchLink><br /><searchLink fieldCode="DE" term="%22NETWORK+routers%22">NETWORK routers</searchLink><br /><searchLink fieldCode="DE" term="%22DATA+packeting%22">DATA packeting</searchLink><br /><searchLink fieldCode="DE" term="%22COMPUTER+architecture%22">COMPUTER architecture</searchLink><br /><searchLink fieldCode="DE" term="%22DETECTORS%22">DETECTORS</searchLink><br /><searchLink fieldCode="DE" term="%22ENERGY+consumption%22">ENERGY consumption</searchLink>
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  Data: We survey recent developments in the design of large-capacity content-addressable memory (CAM). A CAM is a memory that implements the lookup-table function in a single clock cycle using dedicated comparison circuitry. CAMs are especially popular in network routers for packet forwarding and packet classification, but they are also beneficial in a variety of other applications that require high-speed table lookup. The main CAM-design challenge is to reduce power consumption associated with the large amount of parallel active circuitry, without sacrificing speed or memory density. In this paper, we review CAM-design techniques at the circuit level and at the architectural level. At the circuit level, we review low-power matchline sensing techniques and searchline driving approaches. At the architectural level we review three methods for reducing power consumption. [ABSTRACT FROM AUTHOR]
– Name: Abstract
  Label:
  Group: Ab
  Data: <i>Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Type: general
      – SubjectFull: NETWORK routers
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      – SubjectFull: DATA packeting
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