View in EDS

An efficient architecture implementation of a golay code encoder in CMOS 45nm technology.

Saved in:
Bibliographic Details
Title: An efficient architecture implementation of a golay code encoder in CMOS 45nm technology.
Authors: Kumar, Dhanavath Rupa, Naik, Gopiya Naik Sevya
Source: AIP Conference Proceedings; 2024, Vol. 2492 Issue 1, p1-12, 12p
Subject Terms: BINARY codes, TELECOMMUNICATION systems, VIDEO coding, DIGITAL communications
Abstract: This work focuses on an encoding methodology based upon cyclic redundancy checks. High throughput as well as high-speed Golay code encoders may be helpful to digital communication systems. This article discusses methods for generating binary golay code (23, 12). Specifically, CRCs based on LFSRs and hardware architectures based on CRCs There are a few drawbacks to each of these designs. To address these shortcomings, a novel architecture for binary golay code generation (23, 12) has been suggested. Additionally, this article discusses an optimal hardware design for generating expanded golay code (24, 12). Using CMOS45nm technology, a high-speed, small-area, and low-power architecture was developed and validated. The suggested architecture was written in Verilog HDL and then simulated in cadence. The output is also validated with Matlab code and then simulated in MATLAB -R2015. Despite the fact that the CRC encoder is simple to build and reduces the enormous computational burden needed. The suggested approach boosts the transmitting network's efficiency. Our task in this design is to create Quantization coding on the basis of an encoding design utilizing a CRC generating method. This method is used to decrease the difficulty of the circuitry involved in the sending and receiving of signals. [ABSTRACT FROM AUTHOR]
Copyright of AIP Conference Proceedings is the property of American Institute of Physics and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Complementary Index
Description
Abstract:This work focuses on an encoding methodology based upon cyclic redundancy checks. High throughput as well as high-speed Golay code encoders may be helpful to digital communication systems. This article discusses methods for generating binary golay code (23, 12). Specifically, CRCs based on LFSRs and hardware architectures based on CRCs There are a few drawbacks to each of these designs. To address these shortcomings, a novel architecture for binary golay code generation (23, 12) has been suggested. Additionally, this article discusses an optimal hardware design for generating expanded golay code (24, 12). Using CMOS45nm technology, a high-speed, small-area, and low-power architecture was developed and validated. The suggested architecture was written in Verilog HDL and then simulated in cadence. The output is also validated with Matlab code and then simulated in MATLAB -R2015. Despite the fact that the CRC encoder is simple to build and reduces the enormous computational burden needed. The suggested approach boosts the transmitting network's efficiency. Our task in this design is to create Quantization coding on the basis of an encoding design utilizing a CRC generating method. This method is used to decrease the difficulty of the circuitry involved in the sending and receiving of signals. [ABSTRACT FROM AUTHOR]
ISSN:0094243X
DOI:10.1063/5.0196456