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Shared-Semaphored Cache Implementation for Parallel Program Execution in Multi-Core Systems.

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Titel: Shared-Semaphored Cache Implementation for Parallel Program Execution in Multi-Core Systems.
Autoren: Milik, Adam, Walichiewicz, Michał
Quelle: International Journal of Electronics & Telecommunications; 2023, Vol. 69 Issue 2, p371-382, 12p
Schlagwörter: MULTICORE processors, SCHEDULING, COMPILERS (Computer programs), MOTHERBOARDS, COMPUTER interfaces
Abstract: The paper brings forward an idea of multi-threaded computation synchronization based on the shared semaphored cache in the multi-core CPUs. It is dedicated to the implementation of multi-core PLC control, embedded solution or parallel computation of models described using hardware description languages. The shared semaphored cache is implemented as guarded memory cells within a dedicated section of the cache memory that is shared by multiple cores. This enables the cores to speed up the data exchange and seamlessly synchronize the computation. The idea has been verified by creating a multi-core system model using Verilog HDL. The simulation of task synchronization methods allows for proving the benefits of shared semaphored memory cells over standard synchronization methods. The proposed idea enhances the computation in the algorithms that consist of relatively short tasks that can be processed in parallel and requires fast synchronization mechanisms to avoid data race conditions. [ABSTRACT FROM AUTHOR]
Copyright of International Journal of Electronics & Telecommunications is the property of Polish Academy of Sciences and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Label: Title
  Group: Ti
  Data: Shared-Semaphored Cache Implementation for Parallel Program Execution in Multi-Core Systems.
– Name: Author
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  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Milik%2C+Adam%22">Milik, Adam</searchLink><br /><searchLink fieldCode="AR" term="%22Walichiewicz%2C+Michał%22">Walichiewicz, Michał</searchLink>
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  Data: International Journal of Electronics & Telecommunications; 2023, Vol. 69 Issue 2, p371-382, 12p
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  Data: <searchLink fieldCode="DE" term="%22MULTICORE+processors%22">MULTICORE processors</searchLink><br /><searchLink fieldCode="DE" term="%22SCHEDULING%22">SCHEDULING</searchLink><br /><searchLink fieldCode="DE" term="%22COMPILERS+%28Computer+programs%29%22">COMPILERS (Computer programs)</searchLink><br /><searchLink fieldCode="DE" term="%22MOTHERBOARDS%22">MOTHERBOARDS</searchLink><br /><searchLink fieldCode="DE" term="%22COMPUTER+interfaces%22">COMPUTER interfaces</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: The paper brings forward an idea of multi-threaded computation synchronization based on the shared semaphored cache in the multi-core CPUs. It is dedicated to the implementation of multi-core PLC control, embedded solution or parallel computation of models described using hardware description languages. The shared semaphored cache is implemented as guarded memory cells within a dedicated section of the cache memory that is shared by multiple cores. This enables the cores to speed up the data exchange and seamlessly synchronize the computation. The idea has been verified by creating a multi-core system model using Verilog HDL. The simulation of task synchronization methods allows for proving the benefits of shared semaphored memory cells over standard synchronization methods. The proposed idea enhances the computation in the algorithms that consist of relatively short tasks that can be processed in parallel and requires fast synchronization mechanisms to avoid data race conditions. [ABSTRACT FROM AUTHOR]
– Name: Abstract
  Label:
  Group: Ab
  Data: <i>Copyright of International Journal of Electronics & Telecommunications is the property of Polish Academy of Sciences and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.24425/ijet.2023.144373
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      – Code: eng
        Text: English
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        PageCount: 12
        StartPage: 371
    Subjects:
      – SubjectFull: MULTICORE processors
        Type: general
      – SubjectFull: SCHEDULING
        Type: general
      – SubjectFull: COMPILERS (Computer programs)
        Type: general
      – SubjectFull: MOTHERBOARDS
        Type: general
      – SubjectFull: COMPUTER interfaces
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            NameFull: Milik, Adam
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              Text: 2023
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              Y: 2023
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            – TitleFull: International Journal of Electronics & Telecommunications
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