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Modelling, Simulation and Code Generation for Electronic Railway Interlocking Systems.

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Title: Modelling, Simulation and Code Generation for Electronic Railway Interlocking Systems.
Authors: Ghignone, Ramiro Adrian, Falco, Cristian Federico, Larosa, Facundo Santiago, Mendes Gouveia, Hernan Pablo, Chang, Leandro Alejandro, Menendez, Martin Nicolas, Lutenberg, Ariel
Source: IEEE Latin America Transactions; Jan2021, Vol. 19 Issue 1, p155-162, 8p
Abstract: Electronic railway interlockings are critical embedded systems which control the safe operation of train signals. Due to the broad variety of railway network topologies and the high functional safety level required, a flexible solution is needed, capable of taking formal requirements and implementing them accordingly to the required application. The scope of this work is to present an approach in which an automatic code generator transforms the control tables which describe the interlocking logic into functional units written in different programming languages like C or VHDL. The generated code allows its implementation in an embedded system based in a FPGA or a microcontroller. In addition, the project contains a graphical user interface to draw and simulate the behavior of the generated model for verification purposes. The developed tool comprises the entire design flow for interlocking systems and presentes several advantages when compared to previous works. [ABSTRACT FROM AUTHOR]
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Database: Complementary Index
Description
Abstract:Electronic railway interlockings are critical embedded systems which control the safe operation of train signals. Due to the broad variety of railway network topologies and the high functional safety level required, a flexible solution is needed, capable of taking formal requirements and implementing them accordingly to the required application. The scope of this work is to present an approach in which an automatic code generator transforms the control tables which describe the interlocking logic into functional units written in different programming languages like C or VHDL. The generated code allows its implementation in an embedded system based in a FPGA or a microcontroller. In addition, the project contains a graphical user interface to draw and simulate the behavior of the generated model for verification purposes. The developed tool comprises the entire design flow for interlocking systems and presentes several advantages when compared to previous works. [ABSTRACT FROM AUTHOR]
ISSN:15480992
DOI:10.1109/TLA.2021.9423859