Jarollahi, H., Gripon, V., Onizawa, N., & Gross, W. J. (2015). Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(4), 642-653. https://doi.org/10.1109/TVLSI.2014.2316733
Citace podle Chicago (17th ed.)Jarollahi, Hooman, Vincent Gripon, Naoya Onizawa, a Warren J. Gross. "Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, no. 4 (2015): 642-653. https://doi.org/10.1109/TVLSI.2014.2316733.
Citace podle MLA (9th ed.)Jarollahi, Hooman, et al. "Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 4, 2015, pp. 642-653, https://doi.org/10.1109/TVLSI.2014.2316733.