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Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks.

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Titel: Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks.
Autoren: Jarollahi, Hooman, Gripon, Vincent, Onizawa, Naoya, Gross, Warren J.
Quelle: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Apr2015, Vol. 23 Issue 4, p642-653, 12p
Schlagwörter: ALGORITHMS, ASSOCIATIVE storage, ENERGY consumption, SIMULATION methods & models, INTEGRATED circuit design, CMOS logic circuits
Abstract: We propose a low-power content-addressable memory (CAM) employing a new algorithm for associativity between the input tag and the corresponding address of the output data. The proposed architecture is based on a recently developed sparse clustered network using binary connections that on-average eliminates most of the parallel comparisons performed during a search. Therefore, the dynamic energy consumption of the proposed design is significantly lower compared with that of a conventional low-power CAM design. Given an input tag, the proposed architecture computes a few possibilities for the location of the matched tag and performs the comparisons on them to locate a single valid match. TSMC 65-nm CMOS technology was used for simulation purposes. Following a selection of design parameters, such as the number of CAM entries, the energy consumption and the search delay of the proposed design are 8%, and 26% of that of the conventional NAND architecture, respectively, with a 10% area overhead. A design methodology based on the silicon area and power budgets, and performance requirements is discussed. [ABSTRACT FROM AUTHOR]
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Datenbank: Complementary Index
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Abstract:We propose a low-power content-addressable memory (CAM) employing a new algorithm for associativity between the input tag and the corresponding address of the output data. The proposed architecture is based on a recently developed sparse clustered network using binary connections that on-average eliminates most of the parallel comparisons performed during a search. Therefore, the dynamic energy consumption of the proposed design is significantly lower compared with that of a conventional low-power CAM design. Given an input tag, the proposed architecture computes a few possibilities for the location of the matched tag and performs the comparisons on them to locate a single valid match. TSMC 65-nm CMOS technology was used for simulation purposes. Following a selection of design parameters, such as the number of CAM entries, the energy consumption and the search delay of the proposed design are 8%, and 26% of that of the conventional NAND architecture, respectively, with a 10% area overhead. A design methodology based on the silicon area and power budgets, and performance requirements is discussed. [ABSTRACT FROM AUTHOR]
ISSN:10638210
DOI:10.1109/TVLSI.2014.2316733