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A novel design of 1-bit full adders for eliminating voltage step in BBL-PT full adder using 32-nm CNTFET technology.

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Titel: A novel design of 1-bit full adders for eliminating voltage step in BBL-PT full adder using 32-nm CNTFET technology.
Autoren: Tirumalasetty, Venkata Rao1 (AUTHOR) venkatarao.srp@gmail.com, Babulu, K.1 (AUTHOR), Naidu, G. Appala1 (AUTHOR)
Quelle: International Journal of Electronics. Nov2025, Vol. 112 Issue 11, p2386-2408. 23p.
Schlagwörter: CARBON nanotube field effect transistors, COMPUTER logic
Abstract: The full adder is essential for building computing systems like multipliers. Optimizing its design with CNTFET technology enhances low power, speed, and circuit density. This article presents a novel approach to address the challenges in Branch-Based Logic and Pass-Transistor (BBL-PT) based 1-bit full adder. The proposed approach involves the use of alternative modified level restorers, including a current sink, D-CNTFET (Diode connected CNTFET), modified current sink, and source structures. The BBL-PT full adder suffers from a voltage step issue in its output. The proposed solution eliminates this drawback using four alternative restorer structures. For +0.9 V supply voltage at 32-nm CNTFET technology, among all the proposed adder designs, the current sink based adder has a reported power consumption of 0.0845 μW, which is exceptionally low with the propagation delay is specified as 6.127 Ps and the Power-Delay Product (PDP) is 0.5177 aJ. The deliberate use of the current sink restorer in the design contributes to achieving these exceptional performance characteristics. An N-bit parallel adder (N=8, 16 & 32) using the proposed full adders is presented, with performance evaluated at 32-nm CNTFET technology and +0.9 V supply using Mentor Graphics tools. Results highlight its efficiency and superiority over existing solutions. [ABSTRACT FROM AUTHOR]
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Datenbank: Business Source Index
Beschreibung
Abstract:The full adder is essential for building computing systems like multipliers. Optimizing its design with CNTFET technology enhances low power, speed, and circuit density. This article presents a novel approach to address the challenges in Branch-Based Logic and Pass-Transistor (BBL-PT) based 1-bit full adder. The proposed approach involves the use of alternative modified level restorers, including a current sink, D-CNTFET (Diode connected CNTFET), modified current sink, and source structures. The BBL-PT full adder suffers from a voltage step issue in its output. The proposed solution eliminates this drawback using four alternative restorer structures. For +0.9 V supply voltage at 32-nm CNTFET technology, among all the proposed adder designs, the current sink based adder has a reported power consumption of 0.0845 μW, which is exceptionally low with the propagation delay is specified as 6.127 Ps and the Power-Delay Product (PDP) is 0.5177 aJ. The deliberate use of the current sink restorer in the design contributes to achieving these exceptional performance characteristics. An N-bit parallel adder (N=8, 16 & 32) using the proposed full adders is presented, with performance evaluated at 32-nm CNTFET technology and +0.9 V supply using Mentor Graphics tools. Results highlight its efficiency and superiority over existing solutions. [ABSTRACT FROM AUTHOR]
ISSN:00207217
DOI:10.1080/00207217.2025.2450735