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Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography.

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Title: Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography.
Authors: Imana, Jose L.1 (AUTHOR) jluimana@ucm.es, He, Pengzhou2 (AUTHOR) phe@villanova.edu, Bao, Tianyou2 (AUTHOR) tbao@villanova.edu, Tu, Yazheng2 (AUTHOR) ytu1@villanova.edu, Xie, Jiafeng2 (AUTHOR) jiafeng.xie@villanova.edu
Source: IEEE Transactions on Circuits & Systems. Part I: Regular Papers. Aug2022, Vol. 69 Issue 8, p3297-3307. 11p.
Subject Terms: *CRYPTOGRAPHY, ARITHMETIC, POLYNOMIAL rings, ELLIPTIC curve cryptography, SHIFT registers, COMPUTATIONAL complexity, QUANTUM cryptography
Abstract: Ring learning-with-errors (RLWE)-based encryption scheme is a lattice-based cryptographic algorithm that constitutes one of the most promising candidates for Post-Quantum Cryptography (PQC) standardization due to its efficient implementation and low computational complexity. Binary Ring-LWE (BRLWE) is a new optimized variant of RLWE, which achieves smaller computational complexity and higher efficient hardware implementations. In this paper, two efficient architectures based on Linear-Feedback Shift Register (LFSR) for the arithmetic used in Inverted Binary Ring-LWE (InvBRLWE)-based encryption scheme are presented, namely the operation of $A\cdot B+C$ over the polynomial ring $\mathbb {Z}_{q}/(x^{n}+1)$. The first architecture optimizes the resource usage for major computation and has a novel input processing setup to speed up the overall processing latency with minimized input loading cycles. The second architecture deploys an innovative serial-in serial-out processing format to reduce the involved area usage further yet maintains a regular input loading time-complexity. Experimental results show that the architectures presented here improve the complexities obtained by competing schemes found in the literature, e.g., involving 71.23% less area-delay product than recent designs. Both architectures are highly efficient in terms of area-time complexities and can be extended for deploying in different lightweight application environments. [ABSTRACT FROM AUTHOR]
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Abstract:Ring learning-with-errors (RLWE)-based encryption scheme is a lattice-based cryptographic algorithm that constitutes one of the most promising candidates for Post-Quantum Cryptography (PQC) standardization due to its efficient implementation and low computational complexity. Binary Ring-LWE (BRLWE) is a new optimized variant of RLWE, which achieves smaller computational complexity and higher efficient hardware implementations. In this paper, two efficient architectures based on Linear-Feedback Shift Register (LFSR) for the arithmetic used in Inverted Binary Ring-LWE (InvBRLWE)-based encryption scheme are presented, namely the operation of $A\cdot B+C$ over the polynomial ring $\mathbb {Z}_{q}/(x^{n}+1)$. The first architecture optimizes the resource usage for major computation and has a novel input processing setup to speed up the overall processing latency with minimized input loading cycles. The second architecture deploys an innovative serial-in serial-out processing format to reduce the involved area usage further yet maintains a regular input loading time-complexity. Experimental results show that the architectures presented here improve the complexities obtained by competing schemes found in the literature, e.g., involving 71.23% less area-delay product than recent designs. Both architectures are highly efficient in terms of area-time complexities and can be extended for deploying in different lightweight application environments. [ABSTRACT FROM AUTHOR]
ISSN:15498328
DOI:10.1109/TCSI.2022.3169471