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An Efficient Sorting Algorithm and Its Hardware Architecture for General Applications.

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Název: An Efficient Sorting Algorithm and Its Hardware Architecture for General Applications.
Autoři: Nguyen-Ly, Thien-Truong1,2 (AUTHOR) truongnguyen@hcmut.edu.vn, Nguyen, Kim-Anh2,3 (AUTHOR) nkimanh@uhsvnu.edu.vn
Zdroj: Circuits, Systems & Signal Processing. Nov2025, Vol. 44 Issue 11, p8422-8438. 17p.
Témata: *SORTING (Electronic computers), *COMPUTER architecture, *DATA structures, *COMPUTER performance, *SCALABILITY, *FIELD programmable gate arrays
Abstrakt: This work presents a new algorithm and its hardware implementation for full data sorting unit targeting flexibility, low-cost, and low-power consumption. It is able not only to sort in expected order, but also to record the index of each sorted value corresponding to the original input sequence. The recording of the position of the ordered values is a distinctive feature compared to previous works. Moreover, without using input/output constraints, the proposed design is very flexible and easily extensible, resulting in wide usability for many different applications. In addition, by combining partially parallel and serial processing, our proposed architecture can significantly improve hardware performance. The implementation results on Xilinx Kintex-7 Field-programmable gate array (FPGA) show that our work provides remarkable reductions in terms of both hardware resources and power consumption. More precisely, with a 16-input sorter, the proposed design reduces the number of slices from to and the power consumption from to compared to the state-of-the-art implementations. [ABSTRACT FROM AUTHOR]
Databáze: Academic Search Index
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Abstrakt:This work presents a new algorithm and its hardware implementation for full data sorting unit targeting flexibility, low-cost, and low-power consumption. It is able not only to sort in expected order, but also to record the index of each sorted value corresponding to the original input sequence. The recording of the position of the ordered values is a distinctive feature compared to previous works. Moreover, without using input/output constraints, the proposed design is very flexible and easily extensible, resulting in wide usability for many different applications. In addition, by combining partially parallel and serial processing, our proposed architecture can significantly improve hardware performance. The implementation results on Xilinx Kintex-7 Field-programmable gate array (FPGA) show that our work provides remarkable reductions in terms of both hardware resources and power consumption. More precisely, with a 16-input sorter, the proposed design reduces the number of slices from to and the power consumption from to compared to the state-of-the-art implementations. [ABSTRACT FROM AUTHOR]
ISSN:0278081X
DOI:10.1007/s00034-025-03196-5