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Size-configurable 200-MHz low-power SRAM macrocells for MPEG2 video-encoding LSIs: Performance enhancement with embedded registers.

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Title: Size-configurable 200-MHz low-power SRAM macrocells for MPEG2 video-encoding LSIs: Performance enhancement with embedded registers.
Authors: Shibata, Nobutaro1, Morimura, Hiroki1
Source: Electronics & Communications in Japan, Part 2: Electronics. Jan1999, Vol. 82 Issue 1, p1-10. 10p.
Subject Terms: *RANDOM access memory, *LARGE scale integration of circuits, *MPEG (Video coding standard), *VIDEO compression standards, *EMBEDDED computer systems, *COMPLEMENTARY metal oxide semiconductors
Abstract: High-performance SRAM macrocells used in the MPEG2 video-encoding LSI chip sets are described. In designing 13 kinds of SRAMs with different sizes, size-configurable memory architecture is employed to shorten design turnaround time. Input and output registers are embedded in the SRAMs for reducing output delay and the timing margin in the presence of skews between input signals. The increase of access time in the read cycle following a writing cycle is suppressed by avoiding overcharging bitlines during the writing-recovery time. In order to reduce recovery time and power dissipation, sense amplifiers and wordlines are inactivated during the writing- recovery time. A redundant address-decoding scheme is also proposed to reduce the number of unnecessarily activated memory cells when a wordline is selected. A 4K-word × 24-bit SRAM test chip is fabricated with a 0.5-μm CMOS process. The chip demonstrates 200-MHz operation under 3.3-V, 25 °C typical conditions and achieves low power dissipation of 110 mW at the 81-MHz operating frequency used in the MPEG2 video-encoding LSI chip sets. © 1999 Scripta Technica, Electron Comm Jpn Pt 2, 82(1): 1–10, 1999 [ABSTRACT FROM AUTHOR]
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  Data: Size-configurable 200-MHz low-power SRAM macrocells for MPEG2 video-encoding LSIs: Performance enhancement with embedded registers.
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  Data: <searchLink fieldCode="AR" term="%22Shibata%2C+Nobutaro%22">Shibata, Nobutaro</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Morimura%2C+Hiroki%22">Morimura, Hiroki</searchLink><relatesTo>1</relatesTo>
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  Data: <searchLink fieldCode="JN" term="%22Electronics+%26+Communications+in+Japan%2C+Part+2%3A+Electronics%22">Electronics & Communications in Japan, Part 2: Electronics</searchLink>. Jan1999, Vol. 82 Issue 1, p1-10. 10p.
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  Data: *<searchLink fieldCode="DE" term="%22RANDOM+access+memory%22">RANDOM access memory</searchLink><br />*<searchLink fieldCode="DE" term="%22LARGE+scale+integration+of+circuits%22">LARGE scale integration of circuits</searchLink><br />*<searchLink fieldCode="DE" term="%22MPEG+%28Video+coding+standard%29%22">MPEG (Video coding standard)</searchLink><br />*<searchLink fieldCode="DE" term="%22VIDEO+compression+standards%22">VIDEO compression standards</searchLink><br />*<searchLink fieldCode="DE" term="%22EMBEDDED+computer+systems%22">EMBEDDED computer systems</searchLink><br />*<searchLink fieldCode="DE" term="%22COMPLEMENTARY+metal+oxide+semiconductors%22">COMPLEMENTARY metal oxide semiconductors</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: High-performance SRAM macrocells used in the MPEG2 video-encoding LSI chip sets are described. In designing 13 kinds of SRAMs with different sizes, size-configurable memory architecture is employed to shorten design turnaround time. Input and output registers are embedded in the SRAMs for reducing output delay and the timing margin in the presence of skews between input signals. The increase of access time in the read cycle following a writing cycle is suppressed by avoiding overcharging bitlines during the writing-recovery time. In order to reduce recovery time and power dissipation, sense amplifiers and wordlines are inactivated during the writing- recovery time. A redundant address-decoding scheme is also proposed to reduce the number of unnecessarily activated memory cells when a wordline is selected. A 4K-word × 24-bit SRAM test chip is fabricated with a 0.5-μm CMOS process. The chip demonstrates 200-MHz operation under 3.3-V, 25 °C typical conditions and achieves low power dissipation of 110 mW at the 81-MHz operating frequency used in the MPEG2 video-encoding LSI chip sets. © 1999 Scripta Technica, Electron Comm Jpn Pt 2, 82(1): 1–10, 1999 [ABSTRACT FROM AUTHOR]
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RecordInfo BibRecord:
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    Identifiers:
      – Type: doi
        Value: 10.1002/(SICI)1520-6432(199901)82:1<1::AID-ECJB1>3.0.CO;2-3
    Languages:
      – Code: eng
        Text: English
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      Pagination:
        PageCount: 10
        StartPage: 1
    Subjects:
      – SubjectFull: RANDOM access memory
        Type: general
      – SubjectFull: LARGE scale integration of circuits
        Type: general
      – SubjectFull: MPEG (Video coding standard)
        Type: general
      – SubjectFull: VIDEO compression standards
        Type: general
      – SubjectFull: EMBEDDED computer systems
        Type: general
      – SubjectFull: COMPLEMENTARY metal oxide semiconductors
        Type: general
    Titles:
      – TitleFull: Size-configurable 200-MHz low-power SRAM macrocells for MPEG2 video-encoding LSIs: Performance enhancement with embedded registers.
        Type: main
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      – PersonEntity:
          Name:
            NameFull: Shibata, Nobutaro
      – PersonEntity:
          Name:
            NameFull: Morimura, Hiroki
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            – D: 01
              M: 01
              Text: Jan1999
              Type: published
              Y: 1999
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              Value: 8756663X
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              Value: 82
            – Type: issue
              Value: 1
          Titles:
            – TitleFull: Electronics & Communications in Japan, Part 2: Electronics
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