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Size-configurable 200-MHz low-power SRAM macrocells for MPEG2 video-encoding LSIs: Performance enhancement with embedded registers.

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Titel: Size-configurable 200-MHz low-power SRAM macrocells for MPEG2 video-encoding LSIs: Performance enhancement with embedded registers.
Autoren: Shibata, Nobutaro1, Morimura, Hiroki1
Quelle: Electronics & Communications in Japan, Part 2: Electronics. Jan1999, Vol. 82 Issue 1, p1-10. 10p.
Schlagwörter: *RANDOM access memory, *LARGE scale integration of circuits, *MPEG (Video coding standard), *VIDEO compression standards, *EMBEDDED computer systems, *COMPLEMENTARY metal oxide semiconductors
Abstract: High-performance SRAM macrocells used in the MPEG2 video-encoding LSI chip sets are described. In designing 13 kinds of SRAMs with different sizes, size-configurable memory architecture is employed to shorten design turnaround time. Input and output registers are embedded in the SRAMs for reducing output delay and the timing margin in the presence of skews between input signals. The increase of access time in the read cycle following a writing cycle is suppressed by avoiding overcharging bitlines during the writing-recovery time. In order to reduce recovery time and power dissipation, sense amplifiers and wordlines are inactivated during the writing- recovery time. A redundant address-decoding scheme is also proposed to reduce the number of unnecessarily activated memory cells when a wordline is selected. A 4K-word × 24-bit SRAM test chip is fabricated with a 0.5-μm CMOS process. The chip demonstrates 200-MHz operation under 3.3-V, 25 °C typical conditions and achieves low power dissipation of 110 mW at the 81-MHz operating frequency used in the MPEG2 video-encoding LSI chip sets. © 1999 Scripta Technica, Electron Comm Jpn Pt 2, 82(1): 1–10, 1999 [ABSTRACT FROM AUTHOR]
Datenbank: Academic Search Index
Beschreibung
Abstract:High-performance SRAM macrocells used in the MPEG2 video-encoding LSI chip sets are described. In designing 13 kinds of SRAMs with different sizes, size-configurable memory architecture is employed to shorten design turnaround time. Input and output registers are embedded in the SRAMs for reducing output delay and the timing margin in the presence of skews between input signals. The increase of access time in the read cycle following a writing cycle is suppressed by avoiding overcharging bitlines during the writing-recovery time. In order to reduce recovery time and power dissipation, sense amplifiers and wordlines are inactivated during the writing- recovery time. A redundant address-decoding scheme is also proposed to reduce the number of unnecessarily activated memory cells when a wordline is selected. A 4K-word × 24-bit SRAM test chip is fabricated with a 0.5-μm CMOS process. The chip demonstrates 200-MHz operation under 3.3-V, 25 °C typical conditions and achieves low power dissipation of 110 mW at the 81-MHz operating frequency used in the MPEG2 video-encoding LSI chip sets. © 1999 Scripta Technica, Electron Comm Jpn Pt 2, 82(1): 1–10, 1999 [ABSTRACT FROM AUTHOR]
ISSN:8756663X
DOI:10.1002/(SICI)1520-6432(199901)82:1<1::AID-ECJB1>3.0.CO;2-3