Multiprocessors Interconnection Networks

In this chapter, we introduce the different topologies used for interconnecting multiple processors and memory modules. Two schemes are introduced, namely static and dynamic interconnection networks. Static networks form all connections when the system is designed rather than when the connection is...

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Bibliographic Details
Published in:Advanced Computer Architecture and Parallel Processing pp. 19 - 49
Main Authors: El‐Rewini, Hesham, Abd‐El‐Barr, Mostafa
Format: Book Chapter
Language:English
Published: Hoboken, NJ, USA John Wiley & Sons, Inc 17.12.2004
Series:Wiley Series on Parallel and Distributed Computing
Subjects:
banyan networks
crossbar networks
dynamic interconnection networks
hypercube networks
k‐ary n‐cube networks
mesh networks
multiprocessor networks interconnection networks (MINs)
performance analysis of interconnection networks
static interconnection networks
ISBN:9780471467403, 0471467405
Online Access:Get full text
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Summary:In this chapter, we introduce the different topologies used for interconnecting multiple processors and memory modules. Two schemes are introduced, namely static and dynamic interconnection networks. Static networks form all connections when the system is designed rather than when the connection is needed. In a static network, messages must be routed along established links. Dynamic interconnection networks establish connections between two or more nodes on the fly as messages are routed along the links. The hypercube, mesh, and k‐ary n‐cube topologies are introduced as examples for static networks. The bus, crossbar, and multi‐stage interconnection topologies are introduced as examples for dynamic interconnection networks. Our coverage in this chapter concludes with a section on performance evaluation and analysis of the different interconnection networks.
ISBN:9780471467403
0471467405
DOI:10.1002/0471478385.ch2