IMPLEMENTATION OF AN ALGORITHM FOR SQUARE ROOT COMPUTATION IN AN FPGA ARRAY BY USING FIXED POINT REPRESENTATION
Abstract The implementation of the square root computation in an FPGA device is presented in this work. The calculation is not one of convergence type, so the accuracy is very high and there are no conditions or restrictions for the operation to be fulfilled. It also consumes much less hardware surf...
Uloženo v:
| Vydáno v: | Momento číslo 57; s. 41 - 49 |
|---|---|
| Hlavní autoři: | , , |
| Médium: | Journal Article |
| Jazyk: | angličtina portugalština |
| Vydáno: |
Universidad Nacional de Colombia
01.12.2018
|
| Témata: | |
| ISSN: | 0121-4470 |
| On-line přístup: | Získat plný text |
| Tagy: |
Přidat tag
Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!
|
| Abstract | Abstract The implementation of the square root computation in an FPGA device is presented in this work. The calculation is not one of convergence type, so the accuracy is very high and there are no conditions or restrictions for the operation to be fulfilled. It also consumes much less hardware surface than other algorithms for calculating the square root of a number. The number entered is of fixed-point representation, it is parameterizable, that is, two constants N and M can define the size of the number, where N defines the number of bits in the integer part of the number and M defines the number of bits of the fractional part. |
|---|---|
| AbstractList | Abstract The implementation of the square root computation in an FPGA device is presented in this work. The calculation is not one of convergence type, so the accuracy is very high and there are no conditions or restrictions for the operation to be fulfilled. It also consumes much less hardware surface than other algorithms for calculating the square root of a number. The number entered is of fixed-point representation, it is parameterizable, that is, two constants N and M can define the size of the number, where N defines the number of bits in the integer part of the number and M defines the number of bits of the fractional part. |
| Author | Restrepo, Johans Lopez, Jorge H. Tobon, Jorge E. |
| AuthorAffiliation | Universidad de Antioquia |
| AuthorAffiliation_xml | – name: Universidad de Antioquia |
| Author_xml | – sequence: 1 givenname: Jorge H. surname: Lopez fullname: Lopez, Jorge H. organization: Universidad de Antioquia – sequence: 2 givenname: Johans surname: Restrepo fullname: Restrepo, Johans organization: Universidad de Antioquia – sequence: 3 givenname: Jorge E. surname: Tobon fullname: Tobon, Jorge E. organization: Universidad de Antioquia |
| BookMark | eNo1kM9PgzAAhXuYiVN39N5_AGxpR9djnYU1AYoFEndasD8SlwmJ6P8vxHl4eZeX7yXfHVgN4-ABeMQoxltK06fPMR62LGaIMLYCa4QTHFHK0C3YTNMZIZTsOGEErcGoyrqQpaxa0SpdQZ1BUUFR5Nqo9lDCTBvYvHbCSGi0buFel3V33apq2WZ1LqAwRhzh8xF2japymKk3-QJrraoWGlkb2fwfPICb0F8mv7n2Pegy2e4PUaFztRdFNOGUfEeWektTn5Ie28Acst5zGkKSIPzOKSacEW6J2zHXc4YcYiTtbXC8Ryg4FwK5B_Efd7If_jKezuPP1zAfnppFxmmRMbN2i4o5M_EXmWlU1A |
| ContentType | Journal Article |
| Copyright | This work is licensed under a Creative Commons Attribution-NoDerivatives 4.0 International License. |
| Copyright_xml | – notice: This work is licensed under a Creative Commons Attribution-NoDerivatives 4.0 International License. |
| DBID | GPN |
| DOI | 10.15446/mo.n57.70377 |
| DatabaseName | SciELO |
| DatabaseTitleList | |
| DeliveryMethod | fulltext_linktorsrc |
| DocumentTitleAlternate | IMPLEMENTACIÓN DEL ALGORITMO PARA EL CALCULO DE LA RAÍZ CUADRADA EN UN ARREGLO FPGA USANDO REPRESENTACIÓN DE PUNTO FIJO |
| EndPage | 49 |
| ExternalDocumentID | S0121_44702018000200041 |
| GroupedDBID | AAFWJ AFPKN ALMA_UNASSIGNED_HOLDINGS GPN GROUPED_DOAJ RTK |
| ID | FETCH-LOGICAL-s163t-c4ec46e63a1cf7d0cee94ff2201b94139739c3d87da970d0736acfd9a00fddff3 |
| ISICitedReferencesCount | 0 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000441317600004&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| ISSN | 0121-4470 |
| IngestDate | Tue Nov 18 23:14:49 EST 2025 |
| IsDoiOpenAccess | true |
| IsOpenAccess | true |
| IsPeerReviewed | true |
| IsScholarly | true |
| Issue | 57 |
| Keywords | VHDL Operation Square root VLSI FPGA Raíz Cuadrada |
| Language | English Portuguese |
| License | This work is licensed under a Creative Commons Attribution-NoDerivatives 4.0 International License. http://creativecommons.org/licenses/by-nd/4.0 |
| LinkModel | OpenURL |
| MergedId | FETCHMERGED-LOGICAL-s163t-c4ec46e63a1cf7d0cee94ff2201b94139739c3d87da970d0736acfd9a00fddff3 |
| OpenAccessLink | http://dx.doi.org/10.15446/mo.n57.70377 |
| PageCount | 9 |
| ParticipantIDs | scielo_journals_S0121_44702018000200041 |
| PublicationCentury | 2000 |
| PublicationDate | 20181201 |
| PublicationDateYYYYMMDD | 2018-12-01 |
| PublicationDate_xml | – month: 12 year: 2018 text: 20181201 day: 01 |
| PublicationDecade | 2010 |
| PublicationTitle | Momento |
| PublicationTitleAlternate | Momento |
| PublicationYear | 2018 |
| Publisher | Universidad Nacional de Colombia |
| Publisher_xml | – name: Universidad Nacional de Colombia |
| References | Piromsopa, K; Aporntewan, C; Chogsatitvataa, P 2002 Chu, W; Li, Y 2000 Soderquist, P; Leeser, M 1997; 17 Kabuo, H; Taniguchi, T; Miyoshi, A; Yamashita, H; Urano, M; Edamatsu, H; Kuninobu, S 1994; 43 Li, Y; Chu, W 1997 Kaur, J; Grewal, N 2014; 4 Kwon, T.-J; Draper, J 2008 Oberstar, E 2007 Ramamoorthy, C. V; Goodman, J. R; Kim, K. H 1972; 21 Bannur, J; Varma, A 1985 |
| References_xml | – volume: 17 year: 1997 publication-title: IEEE Micro – volume: 21 year: 1972 publication-title: IEEE Transactions on Computers – volume: 4 year: 2014 publication-title: Int. J. Inf. Comp. Tech – start-page: 159 year: 1985 end-page: 165 publication-title: 1985 IEEE 7th Symposium on Computer Arithmetic (ARITH) – year: 2007 publication-title: Fixed-Point Representation and Fractional Math, Report Oberstar Consulting – year: 2002 publication-title: An fpga implementation of a fixed-point square root operation – start-page: 226 year: 1997 end-page: 232 publication-title: Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186) – start-page: 954 year: 2008 end-page: 957 publication-title: 2008 51st Midwest Symposium on Circuits and Systems – start-page: 9 year: 2000 end-page: 16 publication-title: Proceedings 5th Australasian Computer Architecture Conference. ACAC 2000 (Cat. No.PR00512) – volume: 43 year: 1994 publication-title: IEEE Transactions on Computers |
| SSID | ssj0002893730 |
| Score | 2.0478678 |
| Snippet | Abstract The implementation of the square root computation in an FPGA device is presented in this work. The calculation is not one of convergence type, so the... |
| SourceID | scielo |
| SourceType | Open Access Repository |
| StartPage | 41 |
| SubjectTerms | PHYSICS, MULTIDISCIPLINARY |
| Title | IMPLEMENTATION OF AN ALGORITHM FOR SQUARE ROOT COMPUTATION IN AN FPGA ARRAY BY USING FIXED POINT REPRESENTATION |
| URI | http://www.scielo.org.co/scielo.php?script=sci_arttext&pid=S0121-44702018000200041&lng=en&tlng=en |
| WOSCitedRecordID | wos000441317600004&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| journalDatabaseRights | – providerCode: PRVAON databaseName: DOAJ Directory of Open Access Journals issn: 0121-4470 databaseCode: DOA dateStart: 20120101 customDbUrl: isFulltext: true dateEnd: 20201231 titleUrlDefault: https://www.doaj.org/ omitProxy: false ssIdentifier: ssj0002893730 providerName: Directory of Open Access Journals |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwtV1Nj5swELXSbQ-9VK3aqt_yoVIPFmkCJraP7JYkVBtALCslp8jYWNoqC9EmXa3UP18bE0paVdoeekEIGQYxj_HMePwGgI-UCdebFK5jlu0cjJnrcCzGzrjQto_7wvelbTZB4pgulywdDH4c9sLcbkhV0bs7tv2vqtbXtLLN1tl_UHf3UH1Bn2ul66NWuz7eS_HRIj1vKPptQ51kioIYBeezJIvy-QLpqA9dGD82RFmS5OgsWaSX7dgoNmOn6SxAQZYFK3S6QqYvxwxNo2X4BaVJFOcoC43aDgL63u3C0Dns667Ip97a_PRXk3dH82G3ulOaLSrbuq0F5lXn2Od1YcsA7C3hsJ-VGNPfKjwOVSWSSz1NCJvVlKYR36a-Lq54P6Pp6iAW2-4hLdgsZXVrUi0vVjs5W3rTP8y-jxvC4-t6WPlkqI1Y2xrmmEn7wshaG1nmjZtFWEM39gA8dInPaC8e_2ZXYD3S9KrpXrHlaDXSPvdlGZpZbYk3fdckfwqetDEFDCwWnoHBdv8c1Mc4gMkUBjHscAA1DqDFATQ4gD0cwCg2Yw0OYIMDeLqCDQ5ggwPY4AAe4-AFuJyG-dncabtrODvtg-8dgUuBJ-XE42OhiBxpb4lhpVz9bQqGTWDgMeFJSiRnZCT1VDDhQknGRyMlpVLeS3BS1VX5CkCXUM486VEqFC55STkeKVoQpWNjXxH-Gnyy32fd_ie79V908ebeI9-Cx79w9w6c7G--l-_BI3G7v9rdfGhU-RMlD1L_ |
| linkProvider | Directory of Open Access Journals |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=IMPLEMENTATION+OF+AN+ALGORITHM+FOR+SQUARE+ROOT+COMPUTATION+IN+AN+FPGA+ARRAY+BY+USING+FIXED+POINT+REPRESENTATION&rft.jtitle=Momento&rft.au=Lopez%2C+Jorge+H.&rft.au=Restrepo%2C+Johans&rft.au=Tobon%2C+Jorge+E.&rft.date=2018-12-01&rft.pub=Universidad+Nacional+de+Colombia&rft.issn=0121-4470&rft.issue=57&rft.spage=41&rft.epage=49&rft_id=info:doi/10.15446%2Fmo.n57.70377&rft.externalDocID=S0121_44702018000200041 |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0121-4470&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0121-4470&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0121-4470&client=summon |