面向格密码的可配置基-4NTT硬件优化与实现

TP309; 针对数论变换(NTT)优化格密码算法中的多项式乘法问题,以及NTT设计趋向多应用场景的需求,提出了一种面向格密码的可配置基-4 NTT硬件结构.通过分析基-4 NTT/INTT(Inverse NTT)算法流程,设计了高效的现场可编程门阵列(FPGA)整体结构.该结构具备参数化的运行时可配置性和满足多样化需求的编译时可配置性,以流水线方式构建基-4 NTT统一化蝶形单元,并对模除、模约减等关键模块进行优化,提高了计算效率和可配置性.此外,提出可配置多RAM存储优化设计方案及数据存储分配算法,以避免内存冲突、提高数据访问效率.与相关方案的对比及分析表明,以Dilithium算法为例...

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Published in:通信学报 Vol. 45; no. 10; pp. 163 - 179
Main Authors: 周清雷, 韩贺茹, 李斌, 刘宇航
Format: Journal Article
Language:Chinese
Published: 河南省网络密码技术重点实验室,河南 郑州 450001 01.10.2024
郑州大学计算机与人工智能学院,河南 郑州 450001
Subjects:
现场可编程门阵列
格密码
多项式乘法
FPGA
数论变换
butterfly unit
polynomial multiplication
lattice-based cryptography
蝶形单元
NTT
ISSN:1000-436X
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Abstract TP309; 针对数论变换(NTT)优化格密码算法中的多项式乘法问题,以及NTT设计趋向多应用场景的需求,提出了一种面向格密码的可配置基-4 NTT硬件结构.通过分析基-4 NTT/INTT(Inverse NTT)算法流程,设计了高效的现场可编程门阵列(FPGA)整体结构.该结构具备参数化的运行时可配置性和满足多样化需求的编译时可配置性,以流水线方式构建基-4 NTT统一化蝶形单元,并对模除、模约减等关键模块进行优化,提高了计算效率和可配置性.此外,提出可配置多RAM存储优化设计方案及数据存储分配算法,以避免内存冲突、提高数据访问效率.与相关方案的对比及分析表明,以Dilithium算法为例,所提方案不仅具有较高的工作频率,还实现了面积上高达54.3%的优化和吞吐量高达2倍的提升,能够充分发挥FPGA的计算优势.
AbstractList TP309; 针对数论变换(NTT)优化格密码算法中的多项式乘法问题,以及NTT设计趋向多应用场景的需求,提出了一种面向格密码的可配置基-4 NTT硬件结构.通过分析基-4 NTT/INTT(Inverse NTT)算法流程,设计了高效的现场可编程门阵列(FPGA)整体结构.该结构具备参数化的运行时可配置性和满足多样化需求的编译时可配置性,以流水线方式构建基-4 NTT统一化蝶形单元,并对模除、模约减等关键模块进行优化,提高了计算效率和可配置性.此外,提出可配置多RAM存储优化设计方案及数据存储分配算法,以避免内存冲突、提高数据访问效率.与相关方案的对比及分析表明,以Dilithium算法为例,所提方案不仅具有较高的工作频率,还实现了面积上高达54.3%的优化和吞吐量高达2倍的提升,能够充分发挥FPGA的计算优势.
Abstract_FL In response to the complex polynomial multiplication issue in lattice-based cryptography algorithms optimized with number theoretic transform(NTT),as well as the demand for NTT designs catering to multiple application scenarios,a configurable radix-4 NTT hardware architecture for lattice-based cryptography was proposed.By analyzing the radix-4 NTT/INTT(inverse NTT)algorithm process,an efficient FPGA architecture was designed,which parameterized runtime configurability and offered compile-time configurability to meet diverse requirements,a pipeline approach was used to con-struct the radix-4 NTT unified butterfly unit,key algorithmic modules such as modular division and modular reduction were deeply optimized,thereby enhancing computational efficiency and reconfigurability.Additionally,a configurable multi-RAM storage optimization design scheme and data storage allocation algorithm were proposed to avoid memory conflicts and improve data access efficiency.Comparison and analysis with related approaches show that,using the Dilithium algo-rithm as an example,the proposed design not only achieves a high operational frequency but also achieves up to 54.3%im-provement in area and 2 times optimization in throughput,fully leveraging the computational advantages of FPGA.
Author 周清雷
李斌
韩贺茹
刘宇航
AuthorAffiliation 郑州大学计算机与人工智能学院,河南 郑州 450001;河南省网络密码技术重点实验室,河南 郑州 450001
AuthorAffiliation_xml – name: 郑州大学计算机与人工智能学院,河南 郑州 450001;河南省网络密码技术重点实验室,河南 郑州 450001
Author_FL LI Bin
ZHOU Qinglei
HAN Heru
LIU Yuhang
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DocumentTitle_FL Configurable radix-4 NTT hardware optimization and implementation for lattice-based cryptography
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Keywords 现场可编程门阵列
格密码
多项式乘法
FPGA
数论变换
butterfly unit
polynomial multiplication
lattice-based cryptography
蝶形单元
NTT
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PublicationTitle 通信学报
PublicationTitle_FL Journal on Communications
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Publisher 河南省网络密码技术重点实验室,河南 郑州 450001
郑州大学计算机与人工智能学院,河南 郑州 450001
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Snippet TP309; 针对数论变换(NTT)优化格密码算法中的多项式乘法问题,以及NTT设计趋向多应用场景的需求,提出了一种面向格密码的可配置基-4 NTT硬件结构.通过分析基-4...
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