Design Optimization of Low power VLSI Circuits in Deep Submicron Technology

[...]it is vital to look at new device structural model to promote the growth of the VLSI design industry in nano-scale production.. SOItechnologies to shown mote advantages over bulk silicon technology, such as low parasite junction ability, ele vated soft error immunity, removal of CMOS latch-up,...

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Bibliographic Details

Published in:	Annals of the Romanian society for cell biology Vol. 25; no. 4; pp. 4260 - 4264
Main Authors:	Chaitanya, U, Sankar, K Jaya, Murthy, M V Ramana, Naraiah, R, Ahammed, M D Javeed, Balaji, B
Format:	Journal Article
Language:	English
Published:	Arad "Vasile Goldis" Western University Arad, Romania 01.01.2021
Subjects:	Circuits Computer engineering Design optimization Integrated circuits Neural networks Satellite communications Silicon Transistors
ISSN:	2067-3019, 2067-8282
Online Access:	Get full text
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