Design Optimization of Low power VLSI Circuits in Deep Submicron Technology

[...]it is vital to look at new device structural model to promote the growth of the VLSI design industry in nano-scale production.. SOItechnologies to shown mote advantages over bulk silicon technology, such as low parasite junction ability, ele vated soft error immunity, removal of CMOS latch-up,...

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Vydáno v:Annals of the Romanian society for cell biology Ročník 25; číslo 4; s. 4260 - 4264
Hlavní autoři: Chaitanya, U, Sankar, K Jaya, Murthy, M V Ramana, Naraiah, R, Ahammed, M D Javeed, Balaji, B
Médium: Journal Article
Jazyk:angličtina
Vydáno: Arad "Vasile Goldis" Western University Arad, Romania 01.01.2021
Témata:
Circuits
Computer engineering
Design optimization
Integrated circuits
Neural networks
Satellite communications
Silicon
Transistors
ISSN:2067-3019, 2067-8282
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Shrnutí:[...]it is vital to look at new device structural model to promote the growth of the VLSI design industry in nano-scale production.. SOItechnologies to shown mote advantages over bulk silicon technology, such as low parasite junction ability, ele vated soft error immunity, removal of CMOS latch-up, no threshold voltage degradation with body effect, and simply device insulation process [3 ]. Because of its intrinsic structure, SOI has recently drawn specific attention of the short channel impact and improved current drive capacity [4]. at the focus, though, is on the device level. [13] Vijaya Prasad K., Kishore P.V.V., Srinivasa Rao O. (2019), 'Skeleton based viewinvariant human action recognition using convolutional neural networks', Interna-tional Journal of Recent Technology and Engineering, 8(2), PP.4860-4867 [14] Maity R., Maity N.P., Srinivasa Rao K., Guha K., Baishya S. ( 2018) , 'A newcompact analytical model of nanoelectromechanical systems-based capacitive mi-cromachined ultrasonic transducers for pulse echo imaging'Journal of Computa-tional Electronics, 17 (3),PP. 1334- 1342 [15] Aditya M, I Veeraraghava Rao, B. Balaji, John Philip B, Ajay Nagendra N, S Vamsee Krishna," A Novel Low-Power 5th order Analog to Digital Converter for Biomedical Applications", IJITEE, ISSN: 2278-3075, Volume-8 Issue-7,PP: 217-220,May, 2019 [16] B. Balaji, M. Aditya, G. Adithya, M. Sai Priyanka, V. V. S. S. K. Ayyappa Vijay, K. Chandu,: Implementation of Low-Power 1-Bit Hybrid Full adder with Reduced Area", IJITEE, ISSN: 2278-3075, Volume-8 Issue-7,PP:61-64, May, 2019.
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ISSN:2067-3019
2067-8282