Fast, minimal decoding complexity, systematic (13, 8) single-error-correcting codes for on-chip DRAM applications
A fast, minimal decoding complexity, binary systematic single-error-correcting code with one extra parity-bit penalty is presented. It is shown that the new code can be encoded and decoded in combinatorial circuits with minimal decoding complexity. Fast codes are particularly suitable for a 64 bit w...
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| Published in: | Electronics letters Vol. 37; no. 7; pp. 438 - 440 |
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| Main Author: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
29.03.2001
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| ISSN: | 0013-5194 |
| Online Access: | Get full text |
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