Fast, minimal decoding complexity, systematic (13, 8) single-error-correcting codes for on-chip DRAM applications
A fast, minimal decoding complexity, binary systematic single-error-correcting code with one extra parity-bit penalty is presented. It is shown that the new code can be encoded and decoded in combinatorial circuits with minimal decoding complexity. Fast codes are particularly suitable for a 64 bit w...
Uložené v:
| Vydané v: | Electronics letters Ročník 37; číslo 7; s. 438 - 440 |
|---|---|
| Hlavný autor: | |
| Médium: | Journal Article |
| Jazyk: | English |
| Vydavateľské údaje: |
29.03.2001
|
| ISSN: | 0013-5194 |
| On-line prístup: | Získať plný text |
| Tagy: |
Pridať tag
Žiadne tagy, Buďte prvý, kto otaguje tento záznam!
|
| Shrnutí: | A fast, minimal decoding complexity, binary systematic single-error-correcting code with one extra parity-bit penalty is presented. It is shown that the new code can be encoded and decoded in combinatorial circuits with minimal decoding complexity. Fast codes are particularly suitable for a 64 bit word memory organized with single byte boundaries. |
|---|---|
| Bibliografia: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
| ISSN: | 0013-5194 |
| DOI: | 10.1049/el:20010316 |