Fast, minimal decoding complexity, systematic (13, 8) single-error-correcting codes for on-chip DRAM applications
A fast, minimal decoding complexity, binary systematic single-error-correcting code with one extra parity-bit penalty is presented. It is shown that the new code can be encoded and decoded in combinatorial circuits with minimal decoding complexity. Fast codes are particularly suitable for a 64 bit w...
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| Vydáno v: | Electronics letters Ročník 37; číslo 7; s. 438 - 440 |
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| Hlavní autor: | |
| Médium: | Journal Article |
| Jazyk: | angličtina |
| Vydáno: |
29.03.2001
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| ISSN: | 0013-5194 |
| On-line přístup: | Získat plný text |
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| Shrnutí: | A fast, minimal decoding complexity, binary systematic single-error-correcting code with one extra parity-bit penalty is presented. It is shown that the new code can be encoded and decoded in combinatorial circuits with minimal decoding complexity. Fast codes are particularly suitable for a 64 bit word memory organized with single byte boundaries. |
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| Bibliografie: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
| ISSN: | 0013-5194 |
| DOI: | 10.1049/el:20010316 |