Bit‐parallel systolic multiplier over GF(2m) for irreducible trinomials with ASIC and FPGA implementations

Cryptography in digital world must offer integrity and confidentiality using cryptographic algorithms which mainly involve multiplication operation in finite fields. Various algorithms and architectures are proposed in the literature to obtain efficient finite field multiplications in both hardware...

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Vydáno v:	IET circuits, devices & systems Ročník 12; číslo 4; s. 315 - 325
Hlavní autoři:	Mathe, Sudha Ellison, Boppana, Lakshmi
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	Stevenage The Institution of Engineering and Technology 01.07.2018 John Wiley & Sons, Inc
Témata:	Algorithms application specific integrated circuit Application specific integrated circuits ASIC bit-parallel systolic multiplier Complexity computational complexity Computer program integrity cryptographic algorithms Cryptography Data encryption Delay delay complexity analysis Design Field programmable gate arrays field-programmable gate array Fields (mathematics) finite field multiplications FPGA Hardware Integrated circuits irreducible trinomials m-bit systolic multiplier modified interleaved multiplication algorithm Multipliers multiplying circuits Polynomials Power management power-delay products precomputation technique SMT structure
ISSN:	1751-8598, 1751-858X, 1751-8598
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Shrnutí:	Cryptography in digital world must offer integrity and confidentiality using cryptographic algorithms which mainly involve multiplication operation in finite fields. Various algorithms and architectures are proposed in the literature to obtain efficient finite field multiplications in both hardware and software. Here, a modified interleaved multiplication algorithm with reduced computational complexity is proposed based on a novel pre‐computation (PC) technique to perform multiplication over GF(2m) for trinomials. Consequently, an m‐bit systolic multiplier for trinomials (SMT) is designed by employing the proposed algorithm. Hardware and delay complexity analysis is performed and comparison of the proposed SMT structure with similar multipliers available in the literature is presented. The SMT structure achieves ∼28 and 17% improvement in hardware and area‐delay product, respectively, for m = 233 when compared with the best multiplier available in the literature. The functionality of the proposed SMT structure is also verified by implementing on field‐programmable gate array (FPGA) and application‐specific integrated circuit (ASIC) technologies. It can be observed from FPGA and ASIC implementation results that the proposed SMT structure shows improvement in area, power consumption, area‐delay, and power‐delay products when compared with similar multipliers available in the literature.
Bibliografie:	ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14
ISSN:	1751-8598 1751-858X 1751-8598
DOI:	10.1049/iet-cds.2017.0426