Mathe, S. E., & Boppana, L. (2018). Bit‐parallel systolic multiplier over GF(2m) for irreducible trinomials with ASIC and FPGA implementations. IET circuits, devices & systems, 12(4), 315-325. https://doi.org/10.1049/iet-cds.2017.0426
Citace podle Chicago (17th ed.)Mathe, Sudha Ellison, a Lakshmi Boppana. "Bit‐parallel Systolic Multiplier over GF(2m) for Irreducible Trinomials with ASIC and FPGA Implementations." IET Circuits, Devices & Systems 12, no. 4 (2018): 315-325. https://doi.org/10.1049/iet-cds.2017.0426.
Citace podle MLA (9th ed.)Mathe, Sudha Ellison, a Lakshmi Boppana. "Bit‐parallel Systolic Multiplier over GF(2m) for Irreducible Trinomials with ASIC and FPGA Implementations." IET Circuits, Devices & Systems, vol. 12, no. 4, 2018, pp. 315-325, https://doi.org/10.1049/iet-cds.2017.0426.