FPGA Based Highly Efficient AES Implementation
This paper proposes a highly efficient 128-bit AES implementation based on FPGA. The S-box in AES is implemented in composite field, and the Common Sub-expression Elimination (CSE) algorithm is applied to reduce the redundant hardware overhead further more by 42.22% of XOR gates and 52.73% of AND ga...
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| Veröffentlicht in: | Lecture notes in engineering and computer science Jg. 2231/2232; S. 5 |
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| Hauptverfasser: | , , , |
| Format: | Journal Article |
| Sprache: | Englisch |
| Veröffentlicht: |
Hong Kong
International Association of Engineers
25.10.2017
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| Schlagworte: | |
| ISSN: | 2078-0958, 2078-0966 |
| Online-Zugang: | Volltext |
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| Zusammenfassung: | This paper proposes a highly efficient 128-bit AES implementation based on FPGA. The S-box in AES is implemented in composite field, and the Common Sub-expression Elimination (CSE) algorithm is applied to reduce the redundant hardware overhead further more by 42.22% of XOR gates and 52.73% of AND gates. Then we analyze the delay of each arithmetic unit and use pipeline in the proper position to improve the throughput without bringing extra resource consumption. The experiment shows that our strategy can achieve the throughput of 93.54Gbps at the cost of 5081 slices on a Xilinx Virtex-6 XC6VLX240T device. The efficiency of our implementation is 18.41 Mbps/Slice which is much higher than the previous works. |
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| Bibliographie: | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 |
| ISSN: | 2078-0958 2078-0966 |