FPGA Based Highly Efficient AES Implementation

This paper proposes a highly efficient 128-bit AES implementation based on FPGA. The S-box in AES is implemented in composite field, and the Common Sub-expression Elimination (CSE) algorithm is applied to reduce the redundant hardware overhead further more by 42.22% of XOR gates and 52.73% of AND ga...

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Vydané v:	Lecture notes in engineering and computer science Ročník 2231/2232; s. 5
Hlavní autori:	Zhang, Yong, Zhou, Fang, Wu, Ning, Yasir
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	Hong Kong International Association of Engineers 25.10.2017
Predmet:	Gates (circuits)
ISSN:	2078-0958, 2078-0966
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