FPGA Based Highly Efficient AES Implementation

This paper proposes a highly efficient 128-bit AES implementation based on FPGA. The S-box in AES is implemented in composite field, and the Common Sub-expression Elimination (CSE) algorithm is applied to reduce the redundant hardware overhead further more by 42.22% of XOR gates and 52.73% of AND ga...

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Published in:Lecture notes in engineering and computer science Vol. 2231/2232; p. 5
Main Authors: Zhang, Yong, Zhou, Fang, Wu, Ning, Yasir
Format: Journal Article
Language:English
Published: Hong Kong International Association of Engineers 25.10.2017
Subjects:
Gates (circuits)
ISSN:2078-0958, 2078-0966
Online Access:Get full text
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Abstract This paper proposes a highly efficient 128-bit AES implementation based on FPGA. The S-box in AES is implemented in composite field, and the Common Sub-expression Elimination (CSE) algorithm is applied to reduce the redundant hardware overhead further more by 42.22% of XOR gates and 52.73% of AND gates. Then we analyze the delay of each arithmetic unit and use pipeline in the proper position to improve the throughput without bringing extra resource consumption. The experiment shows that our strategy can achieve the throughput of 93.54Gbps at the cost of 5081 slices on a Xilinx Virtex-6 XC6VLX240T device. The efficiency of our implementation is 18.41 Mbps/Slice which is much higher than the previous works.
AbstractList This paper proposes a highly efficient 128-bit AES implementation based on FPGA. The S-box in AES is implemented in composite field, and the Common Sub-expression Elimination (CSE) algorithm is applied to reduce the redundant hardware overhead further more by 42.22% of XOR gates and 52.73% of AND gates. Then we analyze the delay of each arithmetic unit and use pipeline in the proper position to improve the throughput without bringing extra resource consumption. The experiment shows that our strategy can achieve the throughput of 93.54Gbps at the cost of 5081 slices on a Xilinx Virtex-6 XC6VLX240T device. The efficiency of our implementation is 18.41 Mbps/Slice which is much higher than the previous works.
Author Yasir
Wu, Ning
Zhang, Yong
Zhou, Fang
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Snippet This paper proposes a highly efficient 128-bit AES implementation based on FPGA. The S-box in AES is implemented in composite field, and the Common...
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