Nios^{(R)}$ II 임베디드 프로세서를 사용한 병렬처리 시스템의 설계 및 구현

In this thesis, we discuss the implementation of parallel processing system which is able to get a high degree of efficiency(size, cost, performance and flexibility) by using $Nios^{(R)}$ II(32bit RISC(Reduced Instruction Set Computer) processor) embedded processor in DE2-$70^{(R)}$ reference board....

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Bibliographic Details

Published in:	韓國컴퓨터情報學會論文誌 Vol. 14; no. 11; pp. 97 - 103
Main Authors:	이시현, Lee, Si-Hyun
Format:	Journal Article
Language:	Korean
Published:	한국컴퓨터정보학회 01.11.2009
Subjects:	컴퓨터학 RISC Parallel processing system FPGA SoC
ISSN:	1598-849X, 2383-9945
Online Access:	Get full text
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