FPGA-Driven Low Power ECG Analyser with Robust Noise Handling

The increasing necessity for wearable medical devices to keep pace with expanding healthcare demands is driving the requirement for effective processing of biomedical signals. This article introduces an FPGA-based system upgraded for ECG heartbeat detection aimed at solving problems of power consump...

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Vydáno v:2025 5th International Conference on Soft Computing for Security Applications (ICSCSA) s. 762 - 767
Hlavní autoři: Kalaiselvi, A, Jayadharshine, S., Shanthi, K.G., Geeth, R S Kavee, Tamizhmani, T
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 04.08.2025
Témata:
Adders
Biomedical monitoring
ECG(Electrocardiogram) signal processing
Electrocardiography
Field programmable gate arrays
FPGA(Field Programmable Gate Array) implementation
Hardware
hardware footprint reduction
hybrid carry select adder
Hybrid power systems
Medical devices
Medical services
Noise
noise filtering
power efficiency
Real-time systems
Vivado
wearable healthcare devices
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Shrnutí:The increasing necessity for wearable medical devices to keep pace with expanding healthcare demands is driving the requirement for effective processing of biomedical signals. This article introduces an FPGA-based system upgraded for ECG heartbeat detection aimed at solving problems of power consumption, noise suppression, and space constraints. Hybrid Carry Select Adders (CSAs) are utilized to greatly boost computationally velocity, lower the critical path delays, and economize on the hardware resources used. The design has been effectively deployed on the Zybo Z7 FPGA board with Vivado and exhibited good hardware functionality. Experimental findings confirm the system's high accuracy in processing ECG signals, minimal hardware footprint, and enhanced power and timing efficiency. The improved design provides a basis for real-time applications in wearable and portable medical devices.
DOI:10.1109/ICSCSA66339.2025.11171192