Hybrid-NL2SVA: Integrating RAG and Finetuning for LLM-based NL2SVA

SystemVerilog Assertions (SVAs) are critical for verifying the correctness of hardware designs, but manually writing them from natural language property descriptions, i.e., NL2SVA, remains a labor-intensive and error-prone task. Recent advances in large language models (LLMs) offer opportunities to...

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Bibliographic Details

Published in:	2025 ACM/IEEE 7th Symposium on Machine Learning for CAD (MLCAD) pp. 1 - 10
Main Authors:	Xiao, Weihua, Ekberg, Derek, Garg, Siddharth, Karri, Ramesh
Format:	Conference Proceeding
Language:	English
Published:	IEEE 08.09.2025
Subjects:	Aerodynamics Annotations Evaluation Dataset Fine-tuning Hardware design languages Large Language Model Large language models Retrieval augmented generation Semantics Solid modeling Syntactics SystemVerilog Assertion Translation Writing
Online Access:	Get full text
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