Velocity Pausing Particle Swarm Optimization Algorithm based Universal High-Throughput and Low-Complexity LDPC Decoder for Laser Communications

This work presents Lower-Density Parity-Check (LDPC) decoder that is distinguished by its low complexity and highest throughput to fulfil the highest data rate of needs of laser communications and overcome the difficulties caused by propagation channel impairments. Existing techniques have issues wi...

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Vydáno v:2025 IEEE 5th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA) s. 1 - 6
Hlavní autoři: Y, Bhanu Priya, A, Kishore Kumar
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 23.05.2025
Témata:
Approximation algorithms
Complexity theory
Decoding
Inter-Frame Pipeline and Intra-Frame Parallel scheme
Lasers
Low-Density Parity-Check decoder
Message passing
Parity check codes
Particle swarm optimization
Pipelines
Throughput
Velocity Pausing Particle Swarm Optimization Algorithm Unitary Approximate Message Passing Algorithm
Very large scale integration
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Shrnutí:This work presents Lower-Density Parity-Check (LDPC) decoder that is distinguished by its low complexity and highest throughput to fulfil the highest data rate of needs of laser communications and overcome the difficulties caused by propagation channel impairments. Existing techniques have issues with error correction, latency, and resource efficiency. In this manuscript, Velocity Pausing Particle Swarm Optimization Algorithm based Universal High-Throughput with Lower-Complexity Lower-Density Parity-Check Decoder used for Laser Communications (LDPC-LC-VPPSOA) is proposed. The primary goal of this decoder, depending upon Inter-Frame Pipeline with Intra-Frame Parallel (IFPP-IFP) system, is particularly designed to optimize the effectiveness of processing units, most important to enhance in decoding throughput. The performance of IFPP is enhanced through the Unitary Approximate Message Passing (UAMP) approach and the Velocity Pausing Particle Swarm Optimization Algorithm (VPPSOA), differentiating from existing solutions. Furthermore, the decoder uses a message packing approach and lower-complexity data alignment units to efficiently attain IFP. Then the proposed LDPC-LC-VPPSOA method is implemented in Xilinx XCKU060 FPGA and the performance metrics like decoding throughput, hardware complexity and Bit error rate are analyzed. Then, the LDPC-LC-VPPSOA approach attains 18.34%, 16.23%, 19.56% higher decoding throughput, 16.55%, 24.12% and 27.22% lower Hardware Complexity compared with existing techniques like Universal Higher- Throughput and Lower-Complexity Lower-Density Parity-Check Decoder used for Laser Communications (UHTLC-LDPCD-LC), Scalable High-Throughput with Lower-Latency DVB-S2(x) Lower-Density Parity-Check Decoders on SIMD Devices (SHTLL-LDPCD-SIMD) and Highly Reliable with Secure Scheme and Multi-Layer Parallel Lower-Density Parity-Check with Kyber for fist the generation Communications (HRSS-LDPC-KC) respectively.
DOI:10.1109/VLSISATA65374.2025.11070064