Hybrid Encryption/Decryption Embedded System Design Based on ECC, SM3, SM4

In the context of the current diversification of network attacks, it is evident that the traditional single encryption algorithm is no longer sufficient to meet the requisite security standards. Consequently, there is a pressing need to develop more sophisticated and robust data security measures. A...

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Vydáno v:2024 4th International Conference on Communication Technology and Information Technology (ICCTIT) s. 177 - 184
Hlavní autoři: Yang, Peng, Huang, Haisheng, Li, Xin, Zhang, Chi, Zhu, Zhenxing, Zhao, Qi
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 27.12.2024
Témata:
ECC
Elliptic curve cryptography
embedded system
Embedded systems
Encryption
Hardware
hardware-software co-design
hybrid encryption/decryption system
Hybrid power systems
Power demand
Security
SM3
SM4
Software
Time complexity
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Shrnutí:In the context of the current diversification of network attacks, it is evident that the traditional single encryption algorithm is no longer sufficient to meet the requisite security standards. Consequently, there is a pressing need to develop more sophisticated and robust data security measures. Accordingly, this paper proposes an embedded design scheme based on Elliptic Curve Cryptography (ECC), SM3, SM4 hybrid encryption/decryption system. This utilizes the ECC and SM3 modules to generate SM4 encryption/decryption keys by means of hardware-software co-design, the plaintext/ciphertext is transmitted to the SM4 encryption module via the Advanced High-Performance Bus (AHB) for encryption/decryption of the plaintext/ciphertext. Furthermore, the SM3 module is a joint effort between hardware and software, which minimizes the consumption of hardware resources. The encryption/decryption system is capable of markedly enhancing the security coefficient while simultaneously considering the security of asymmetric encryption and the high speed of symmetric encryption, while also offering the functionality of information verification. The experimental results show that the hardware structure of the hybrid encryption/decryption system designed in this paper is streamlined, the resource utilization is high, the power consumption is relatively low, but the execution rate decreases to a certain extent compared with the pure FPGA hardware, and its resource overhead and time complexity have different degrees of advantages compared with other related references work.
DOI:10.1109/ICCTIT64404.2024.10928500