Low-Power Reconfigurable FIR Filter HDL Design

This article discusses the process of HDL (hardware description language) design and testing of reconfigurable FIR filter optimized for low-power consumption in nanoscale CMOS technology. The maximum number of coefficients and used numerical data representation can be set during synthesis. The end-u...

Full description

Saved in:

Bibliographic Details
Published in:	Applied Electronics, AE, International Conference on pp. 1 - 6
Main Authors:	Bagin, Richard, Nagy, Lukas, Stopjakova, Viera
Format:	Conference Proceeding
Language:	English
Published:	IEEE 08.09.2025
Subjects:	Fabrication Finite impulse response filters FIR filter Flip-flops floating-point Hardware Hardware design languages HDL MATLAB MATLAB app designer Nanoscale devices Power demand Production Q-format SystemVerilog Testing
ISSN:	1805-9597
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!

Be the first to leave a comment!