Low-Power Reconfigurable FIR Filter HDL Design
This article discusses the process of HDL (hardware description language) design and testing of reconfigurable FIR filter optimized for low-power consumption in nanoscale CMOS technology. The maximum number of coefficients and used numerical data representation can be set during synthesis. The end-u...
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| Published in: | Applied Electronics, AE, International Conference on pp. 1 - 6 |
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| Main Authors: | , , |
| Format: | Conference Proceeding |
| Language: | English |
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IEEE
08.09.2025
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| Subjects: | |
| ISSN: | 1805-9597 |
| Online Access: | Get full text |
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| Abstract | This article discusses the process of HDL (hardware description language) design and testing of reconfigurable FIR filter optimized for low-power consumption in nanoscale CMOS technology. The maximum number of coefficients and used numerical data representation can be set during synthesis. The end-user is then capable of changing the number of active coefficients (filter order) and their value. All flip-flops can be rearranged into 1-bit scan-chain for production test, and it can also be used for filter debugging. MATLAB application was developed for easier interaction with the FIR filter. It allows the user to set the coefficients, process the samples, scan and display the contents of flip-flops. |
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| AbstractList | This article discusses the process of HDL (hardware description language) design and testing of reconfigurable FIR filter optimized for low-power consumption in nanoscale CMOS technology. The maximum number of coefficients and used numerical data representation can be set during synthesis. The end-user is then capable of changing the number of active coefficients (filter order) and their value. All flip-flops can be rearranged into 1-bit scan-chain for production test, and it can also be used for filter debugging. MATLAB application was developed for easier interaction with the FIR filter. It allows the user to set the coefficients, process the samples, scan and display the contents of flip-flops. |
| Author | Stopjakova, Viera Bagin, Richard Nagy, Lukas |
| Author_xml | – sequence: 1 givenname: Richard surname: Bagin fullname: Bagin, Richard email: richard.bagin@stuba.sk organization: Institute of Electronics and Photonics, Slovak University of Technology,Bratislava,Slovakia – sequence: 2 givenname: Lukas surname: Nagy fullname: Nagy, Lukas email: lukas.nagy@stuba.sk organization: Institute of Electronics and Photonics, Slovak University of Technology,Bratislava,Slovakia – sequence: 3 givenname: Viera surname: Stopjakova fullname: Stopjakova, Viera email: viera.stopjakova@stuba.sk organization: Institute of Electronics and Photonics, Slovak University of Technology,Bratislava,Slovakia |
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| Snippet | This article discusses the process of HDL (hardware description language) design and testing of reconfigurable FIR filter optimized for low-power consumption... |
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| SubjectTerms | Fabrication Finite impulse response filters FIR filter Flip-flops floating-point Hardware Hardware design languages HDL MATLAB MATLAB app designer Nanoscale devices Power demand Production Q-format SystemVerilog Testing |
| Title | Low-Power Reconfigurable FIR Filter HDL Design |
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