A Fully Integrated Mixed-Signal Compute-In-Memory Accelerator for Solving Arbitrary Order Boolean Satisfiability Problems

This paper presents a mixed-signal In-Memory Computing (IMC) accelerator with 256 \times 128 10T bi-directional SRAM array in 55 nm CMOS process, for solving arbitrary-order KBoolean Satisfiability (K-SAT) problems. It achieves nearly an order of magnitude faster solution times compared to other sin...

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Bibliographic Details

Published in:	Digest of technical papers - Symposium on VLSI Technology pp. 1 - 3
Main Authors:	Bhattacharya, Tinish, Kwon, Dongseok, Hutchinson, George Higgins, Zhang, Xiangyi, Rozada, Ignacio, Strukov, Dmitri
Format:	Conference Proceeding
Language:	English
Published:	JSAP 08.06.2025
Subjects:	Bidirectional control CMOS process Cryptography In-memory computing Random access memory Very large scale integration
ISSN:	2158-9682
Online Access:	Get full text
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